EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 340
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Enhanced PLLs
1–30
Stratix Device Handbook, Volume 2
CLK4p/n
CLK5p/n
CLK6p/n
CLK7p/n
CLK12p/n
CLK13p/n
CLK14p/n
CLK15p/n
PLL5_FBp/n
PLL6_FBp/n
PLLENABLE
Table 1–9. Enhanced PLL Pins (Part 1 of 2)
Pin
f
Single-ended or differential pins that can drive the inclk port for PLL 6.
Single-ended or differential pins that can drive the inclk port for PLL 6.
Single-ended or differential pins that can drive the inclk port for PLL 12.
Single-ended or differential pins that can drive the inclk port for PLL 12.
Single-ended or differential pins that can drive the inclk port for PLL 11.
Single-ended or differential pins that can drive the inclk port for PLL 11.
Single-ended or differential pins that can drive the inclk port for PLL 5.
Single-ended or differential pins that can drive the inclk port for PLL 5.
Single-ended or differential pins that can drive the fbin port for PLL 5.
Single-ended or differential pins that can drive the fbin port for PLL 6.
Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do not
use this pin, connect it to ground.
With down-spread modulation, the peak of the modulated waveform is
the actual target frequency. Therefore, the system never exceeds the
maximum clock speed. To maintain reliable communication, the entire
system/subsystem should use the Stratix or Stratix GX device as the clock
source. Communication could fail if the Stratix or Stratix GX logic array
is clocked by the spread-spectrum clock, but the data it receives from
another device is not.
Since spread spectrum affects the m counter values, all spread-spectrum
PLL outputs are affected. Therefore, if only one spread-spectrum signal is
needed, the clock signal should use a separate PLL without other outputs
from that PLL.
No special considerations are needed when using spread spectrum with
the clock switchover feature. This is because the clock switchover feature
does not affect the m and n counter values, which are the counter values
that are switching when using spread spectrum.
PLL Reconfiguration
See AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX
Devices for information on PLL reconfiguration.
Enhanced PLL Pins
Table 1–9
PLLs. For inclk port connections to pins see
shows the physical pins and their purpose for the Enhanced
Description
“Clocking” on page
Altera Corporation
July 2005
1–39.
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