EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 350

IC STRATIX FPGA 10K LE 780-FBGA

EP1S10F780I6N

Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S10F780I6N

Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Part Number:
EP1S10F780I6N
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0
Clocking
1–40
Stratix Device Handbook, Volume 2
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. All resources within the device—IOEs, LEs, DSP blocks, and
all memory blocks—can use the global clock networks as clock sources.
These resources can also be used for control signals, such as clock enables
and synchronous or asynchronous clears fed from the external pin.
Internal logic can also drive the global clock networks for internally
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout.
pins driving global clock networks.
Figure 1–19. Global Clocking
Regional Clock Network
There are four regional clock networks within each quadrant of the
Stratix or Stratix GX device that are driven by the same dedicated
CLK[15..0] input pins or from PLL outputs. From a top view of the
silicon, RCLK[0..3] are in the top-left quadrant, RCLK[8..11] are in
the top-right quadrant, RCLK[4..7] are in the bottom-left quadrant, and
CLK[3..0]
Global Clock [15..0]
CLK[7..4]
Figure 1–19
CLK[15..12]
Global Clock [15..0]
shows the 16 dedicated CLK
Altera Corporation
CLK[11..8]
July 2005

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