EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 343

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
inclk1
pllena
areset
pfdena
clk[2..0]
locked
Table 1–10. Fast PLL Input Signals
Table 1–11. Fast PLL Output Signals
Name
Name
Reference clock input to PLL
Enable pin for enabling or disabling all or a set of
PLLs – active high
Signal used to reset the PLL which re-
synchronizes all the counter outputs active high
Enables the up/down outputs from the phase-
frequency detector active high
PLL outputs driving regional or global clock
Lock output from lock detect circuit active high
Figure 1–18
Figure 1–18. Fast PLL Ports & Physical Destinations
Notes to
(1)
(2)
Tables 1–10
This input pin is shared by all enhanced and fast PLLs.
This input pin is either single-ended or differential.
Figure
Description
Description
(1)
(2)
Physical Pin
Signal Driven by Internal Logic
Signal Driven to Internal Logic
Internal Clock Signal
and
shows all possible ports related to fast PLLs.
1–18:
1–11
General-Purpose PLLs in Stratix & Stratix GX Devices
show the description of all fast PLL ports.
pllena
inclk0
areset
pfdena
Fast PLL Signals
Pin
Pin
Logic array
Logic array
Stratix Device Handbook, Volume 2
PLL counter
PLL lock
detect
Source
Source
PFD
PLL control signal
PLL control signal
PFD
clk[2..0]
locked
Internal clock
Logic array
Destination
Destination
1–33