EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 499
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
EP1S10F780I6N
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Figure 5–19. SERDES Function Timing Diagram with Data-Realignment Operation
Altera Corporation
July 2005
Serial data
×8 clock
×1 clock
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
D7
D0
D1
D2
Generating the TXLOADEN Signal
The TXLOADEN signal controls the transfer of data between the SERDES
circuitry and the logic array when data realignment is used. To prevent
the interruption of the TXLOADEN signal during data realignment, both k
and v counter are used.
In normal operation the TXLOADEN signal is generated by the k counter.
However, during the data-realignment operation this signal is generated
by either counter. When the k counter is used for realignment, the
D3
D2
D3
D4
D5
D6
D7
D0
D1
D4
D5
D6
High-Speed Differential I/O Interfaces in Stratix Devices
D7
D0
D1
D2
D3
Stratix Device Handbook, Volume 2
D3
D4
D5
D6
D7
D0
D1
D2
D4
D5
D6
D7
D0
D1
D3
D4
D5
D6
D7
D0
D1
D2
5–27
D2
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