EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 738
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Manufacturer
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Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Configuration Schemes
11–20
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
t
t
f
t
CF2CD
CF2ST0
CF2ST1
CFG
STATUS
CF2CK
ST2CK
DSU
DH
CH
CL
CLK
MAX
CD2UM
Table 11–8. PS Timing Parameters for Stratix & Stratix GX Devices
Symbol
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.
Table
nCONFIG
nCONFIG
nCONFIG
nCONFIG
nSTATUS
nCONFIG
nSTATUS
Data setup time before rising edge on
Data hold time after rising edge on
DCLK
DCLK
DCLK
DCLK
CONF_DONE
11–8:
high time
low time
period
maximum frequency
low to
low to
low pulse width
low pulse width
high to first rising edge on
high to first rising edge on
high to
high to user mode
CONF_DONE
nSTATUS
nSTATUS
low
Parameter
high
low
(1)
DCLK
DCLK
DCLK
DCLK
Min
40
10
40
10
1
7
0
4
4
6
Altera Corporation
40
40
Max
800
800
100
20
(2)
(2)
July 2005
Units
MHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
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