EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 704

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

PLLs & Clock Networks
10–20
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) Stratix GX EP1SGX10 and EP1SGX25 contain two. EP1SGX40 contains four.
(11) Stratix GX supports clock rates of 1 Gbps using DPA.
Internal clock outputs per
PLL
External clock outputs per
PLL
Phase Shift
Time shift
M counter values
N counter values
PLL clock input sharing
T1/E1 rate conversion
Table 10–6. Stratix & Stratix GX PLL vs. APEX II, APEX 20KE & APEX 20KC PLL Features (Part 2 of 2)
EP20K200E and smaller devices only have two general-purpose PLLs. EP20K400E and larger devices have two
LVDS PLLs and four general-purpose PLLs. For more information, see AN 115: Using the ClockLock & ClockBoost
PLL Features in APEX Devices.
The maximum input frequency for Stratix and Stratix GX enhanced PLLs depends on the I/O standard used with
that input clock pin. For more information, see the Stratix Device Family Data Sheet section of the Stratix Device
Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1.
Fast PLLs 1, 2, 3, and 4 have three internal clock output ports per PLL. Fast PLLs 7, 8, 9, and 10 have two internal
clock output ports per PLL.
Every Stratix device has two enhanced PLLs with eight single-ended or four differential outputs each. Two
additional enhanced PLLs in EP1S80, EP1S60, and EP1S40 devices each have one single-ended output.
Any I/O pin can be driven by the fast PLL global or regional outputs as an external clock output pin.
The smallest phase shift unit is determined by the voltage-controlled oscillator (VCO) period divided by 8.
There is a maximum of 3 ns between any two PLL clock outputs.
The T1 clock frequency is 1.544 MHz and the E1 clock frequency is 2.048 MHz, which violates the minimum clock
input frequency requirement of the Stratix PLL.
Stratix GX EP1SGX10 and EP1SGX25 contain two. EP1SGX40 contains four.
Table
Feature
10–6:
(8)
Enhanced PLLs
Stratix and Stratix GX devices provide up to four enhanced PLLs with
advanced PLL features. In addition to the feature changes mentioned in
Table
250-ps increments
1 to 512
6
Four
differential/eight
singled-ended or
one single-ended
(4)
Down to 160-ps
increments
for ± 3 ns
1 to 512
No
No
Enhanced PLLs
10–6, Stratix and Stratix GX device PLLs include many new,
Stratix & Stratix GX
(7)
(6)
3
Yes
Down to 125-ps
increments
No
1 to 32
N/A
Yes
No
(3)
Fast PLLs
(5)
(6)
2
1
500-ps to 1-ns
resolution
No
1 to 160
1 to 16
Yes
Yes
APEX II PLLs
Altera Corporation
2
1
0.4- to 1-ns
resolution
No
2 to 160
1 to 16
Yes
Yes
APEX 20KC PLLs
APEX 20KE &
July 2005