EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 487
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 487 of 864
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Figure 5–11. SDR Clock-to-Data Relationship
Figure 5–12. SDR Receiver & Transmitter Circuit Connection
Altera Corporation
July 2005
inclock
data rate = 624 Mbps
SDR
624 MHz
rx_d[15]
rxclk
rx_d[0]
XX
Stratix SERDES SDR Receiver
LVDS PLL
Channel
Channel
input clock × W
15
0
Serial-to-Parallel
Serial-to-Parallel
Register
Register
B0
automatically assigns a seventeenth channel as the transmitter clock
output. You can edge- or center-align the transmitter clock output by
selecting the default PLL phase or selecting the 90° phase of the PLL
output. On the receiver side, the clock signal is connected to the receiver
PLL's clock input, and you can assign identical clock-to-data alignment.
The multiplication factor W is calculated automatically. The data rate is
dividing by the input clock frequency to calculate the W factor. The
deserialization factor J may be 4, 7, 8, or 10.
Figure 5–11
center aligned with respect to data.
between the receiver and transmitter circuits.
rxloaden
Register
Register
Parallel
Parallel
shows an SDR clock-to-data timing relationship, with clock
8
8
High-Speed Differential I/O Interfaces in Stratix Devices
Stratix
Logic
Array
B1
LVDS PLL
8
8
txloaden
Stratix SERDES SDR Transmitter
Register
Register
Parallel
Parallel
Figure 5–12
input clock × W
Stratix Device Handbook, Volume 2
Parallel-to-Serial
Parallel-to-Serial
Register
Register
shows the connection
B2
Channel
Channel
Channel
15
16
0
data rate = 624 Mbps
624 MHz
624 MHz
txclk_out
txclk_in
tx_d[15]
tx_d[0]
B3
5–15
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