EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 723

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
PORSEL Pins
PORSEL is a dedicated input pin used to select POR delay times of 2 ms
or 100 ms during power-up. When the PORSEL pin is connected to
ground, the POR time is 100 ms; when the PORSEL pin is connected to
VCC, the POR time is 2 ms. There is an internal 2.5-k pull-down resistor
on PORSEL. Therefore if you are using a pull-up resistor to pull up this
signal, you need to use a 1-k resistor.
When using enhanced configuration devices to configure Stratix devices,
make sure that the PORSEL setting of the Stratix device is the same or
faster than the PORSEL setting of the enhanced configuration device. If
the FPGA is not powered up after the enhanced configuration device exits
POR, the CONF_DONE signal will be high since the pull-up resistor is
pulling this signal high. When the enhanced configuration device exits
POR, OE of the enhanced configuration device is released and pulled
high by a pull-up resistor. Since the enhanced configuration device sees
its nCS/CONF_DONE signal also high, it enters a test mode. Therefore, you
must ensure the FPGA powers up before the enhanced configuration
device exits POR.
For more margin, the 100-ms setting can be selected when using an
enhanced configuration device to allow the Stratix FPGA to power-up
before configuration is attempted (see
nIO_PULLUP Pins
The nIO_PULLUP pin enables a built-in weak pull-up resistor to pull all
user I/O pins to VCCIO before and during device configuration. If
nIO_PULLUP is connected to V
ups on all user I/O pins and all dual-purpose pins are disabled. If
connected to ground, the pull-ups are enabled during configuration. The
nIO_PULLUP pin can be pulled to 1.5, 1.8, 2.5, or 3.3-V for a logic level
high. There is an internal 2.5-k pull-down resistor on nIO_PULLUP.
Therefore, if you are using a pull-up resistor to pull up this signal, you
need to use a 1-k resistor.
Table 11–4. PORSEL Settings
PORSEL Settings
GND
V
CC
CC
Configuring Stratix & Stratix GX Devices
during configuration, the weak pull-
Table
Stratix Device Handbook, Volume 2
11–4).
POR Time (ms)
100
2
11–5