C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 121
C8051F411-GMR
Manufacturer Part Number
C8051F411-GMR
Description
Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F410DK.pdf
(270 pages)
Specifications of C8051F411-GMR
Processor Series
C8051F4x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
20
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F410DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 20 Channel
On-chip Dac
12 bit, 2 Channel
Package
28QFN EP
Device Core
8051
Family Name
C8051F41x
Maximum Speed
50 MHz
Ram Size
2.25 KB
Operating Supply Voltage
1.8|2.5|3.3|5 V
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F411-GMR
Manufacturer:
SiliconL
Quantity:
3 000
Part Number:
C8051F411-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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14. Cyclic Redundancy Check Unit (CRC0)
C8051F41x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit
or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts the
16-bit or 32-bit result to an internal register. The internal result register may be accessed indirectly using
the CRC0PNT bits and CRC0DAT register, as shown in Figure 14.1. CRC0 also has a bit reverse register
for quick data manipulation.
14.1. 16-bit CRC Algorithm
The C8051F41x CRC unit calculates the 16-bit CRC MSB-first, using a poly of 0x1021. The following
describes the 16-bit CRC algorithm performed by the hardware:
Step 1. XOR the most-significant byte of the current CRC result with the input byte. If this is the
Step 2a. If the MSB of the CRC result is set, left-shift the CRC result, and then XOR the CRC
Step 2b. If the MSB of the CRC result is not set, left-shift the CRC result.
Step 3. Repeat at Step 2a for the number of input bits (8).
first iteration of the CRC unit, the current CRC result will be the set initial value (0x0000 or
0xFFFF).
result with the polynomial (0x1021).
CRC0PNT1
CRC0PNT0
CRC0SEL
CRC0INIT
CRC0VAL
Figure 14.1. CRC0 Block Diagram
CRC0IN
8
Rev. 1.1
CRC Engine
8
RESULT
4 to 1 MUX
8
32
8
8
8
C8051F410/1/2/3
CRC0DAT
121
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