C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 204

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

C8051F410/1/2/3
21.5.4. Slave Transmitter Mode
Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH
= 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a
slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an
interrupt is generated and the ACKRQ bit is set. Software responds to the received slave address with an
ACK, or ignores the received slave address with a NACK. If the received slave address is ignored, slave
interrupts will be inhibited until a START is detected. If the received slave address is acknowledged, data
should be written to SMB0DAT to be transmitted. The interface enters Slave Transmitter Mode, and trans-
mits one or more bytes of data. After each byte is transmitted, the master sends an acknowledge bit; if the
acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If the acknowledge bit is
a NACK, SMB0DAT should not be written to before SI is cleared (Note: an error condition may be gener-
ated if SMB0DAT is written following a received NACK while in Slave Transmitter Mode). The interface
exits Slave Transmitter Mode after receiving a STOP. Note that the interface will switch to Slave Receiver
Mode if SMB0DAT is not written following a Slave Transmitter interrupt. Figure 21.8 shows a typical Slave
Transmitter sequence. Two transmitted data bytes are shown, though any number of bytes may be trans-
mitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode.
21.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the
shown response options are only the typical responses; application-specific procedures are allowed as
long as they conform to the SMBus specification. Highlighted responses are allowed but do not conform to
the SMBus specification.
204
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 21.8. Typical Slave Transmitter Sequence
SLA
Interrupt
R
A
Data Byte
Rev. 1.1
Interrupt
A
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Data Byte
Interrupt
N
Interrupt
P