C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 189

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

L0: mov A, RTC0ADR
L1: mov A, RTC0ADR
L2: mov A, RTC0ADR
L3: mov A, RTC0ADR
L4: mov A, RTC0ADR
To reduce the number of instructions necessary to read and write sections of the 64-byte RAM, the RAMA-
DDR register automatically increments after each write or read. The following C example initializes the
entire 64-byte RAM to 0xA5 and copies this value from the RAM to an array using the auto-increment fea-
ture:
// in 'C':
unsigned char RAM_data[64] = 0x00;
unsigned char addr;
// Unlock smaRTClock, enable smaRTClock
// Write to the entire smaRTClock RAM
RTC0ADR = 0x0E;// address the RAMADDR register
RTC0DAT = 0x00;// write the address of 0x00 to RAMADDR
while ((RTC0ADR & 0x80) == 0x80);
RTC0ADR = 0x0F;// address the RAMDATA register
for (addr = 0; addr < 64; addr++)
{
}
// Read from the entire smaRTClock RAM
RTC0ADR = 0x0E;// address the RAMADDR register
RTC0DAT = 0xA5; // write 0xA5 to every RAM address
while ((RTC0ADR & 0x80) == 0x80);// poll on the BUSY bit
; Enable the smaRTClock
mov RTC0ADR, #06h ; address the RTC0CN register
mov RTC0DAT, #080h ; enable the smaRTClock
jb ACC.7, L0
; Write to the smaRTClock RAM
mov RTC0ADR, #0Eh; address the RAMADDR register
mov RTC0DAT, #20h; write the address of 0x20 to RAMADDR
jb ACC.7, L1
mov RTC0ADR, #0Fh; address the RAMDATA register
mov RTC0DAT, #0A5h; write 0xA5 to RAM address 0x20
jb ACC.7, L2
; Read from the smaRTClock RAM
mov RTC0ADR, #0Eh; address the RAMADDR register
mov RTC0DAT, #20h; write the address of 0x20 to RAMADDR
jb ACC.7, L3
mov RTC0ADR, #0Fh
orl RTC0ADR, #80h
jb ACC.7, L4
movR0, #80h
mov@R0, RTC0DAT
; the 128-byte internal RAM
; poll on the BUSY bit
; poll on the BUSY bit
; poll on the BUSY bit
; poll on the BUSY bit
; read the value of RAM address 0x20 into 
; poll on the BUSY bit
; address the RAMDATA register
; initiate a read of the RAMDATA register
// poll on the BUSY bit
Rev. 1.1
C8051F410/1/2/3
189