C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 177

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

20. smaRTClock (Real Time Clock)
C8051F41x devices include a low power smaRTClock Peripheral (Real Time Clock). The smaRTClock has
a dedicated 32 kHz oscillator that can be configured for use with or without a crystal, a 47-bit smaRTClock
timer with alarm, a backup supply regulator and 64 bytes of battery-backed SRAM. When the backup sup-
ply voltage (V
ply voltage (V
The smaRTClock allows a maximum of 137 year 47-bit independent time-keeping when used with a
32.768 kHz Watch Crystal and backup supply voltage of at least 1V. The switchover logic powers smaRT-
Clock from the backup supply when the voltage at V
Alarm and Missing Clock Detector can interrupt the CIP-51, wake the internal oscillator from SUSPEND
mode, or generate a device reset if the smaRTClock timer reaches a pre-set value or the oscillator stops.
Backup RAM
Regulator
V
Backup
XTAL4
DD
RTC-BACKUP
RTC-BACKUP
) is lost.
64B
smaRTClock State Machine
smaRTClock Oscillator
) is powered, the smaRTClock peripheral remains fully functional if the core sup-
Switchover
Figure 20.1. smaRTClock Block Diagram
Logic
XTAL3
CAPTUREn
RAMADDR
RAMDATA
Registers
RTC0XCN
ALARMn
RTC0CN
Internal
Interrupt
Rev. 1.1
RTC-BACKUP
smaRTClock
smaRTClock
Registers
RTC0ADR
Interface
RTC0KEY
RTC0DAT
is greater than V
47-Bit
Timer
C8051F410/1/2/3
DD
. The smaRTClock
V
DD
177