C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 31

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

1.8.
C8051F41x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit
or 32-bit polynomial. CRC0 accepts a stream of 8-bit data and outputs a 16-bit or 32-bit result. CRC0 also
has a hardware bit reverse feature for quick data manipulation.
1.9.
C8051F41x devices include an on-chip low dropout voltage regulator (REG0). The input to REG0 at the
V
enabled, the output of REG0 powers the device and drives the V
to power external devices connected to V
1.10. Serial Ports
The C8051F41x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate
configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware
and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
REGIN
Port I/O
Port I/O
Pins
Pins
pin can be as high as 5.25 V. The output can be selected by software to 2.0 V or 2.5 V. When
Cyclic Redundancy Check Unit
Voltage Regulator
Figure 1.9. Comparators Block Diagram
+
-
+
-
VDD
VDD
GND
GND
DD
.
Decision
Rev. 1.1
Reset
Tree
(SYNCHRONIZER)
(SYNCHRONIZER)
D
D
SET
CLR
SET
CLR
Q
Q
Q
Q
DD
D
D
SET
CLR
SET
CLR
Interrupt
Interrupt
Q
Q
Q
Q
pin. The voltage regulator can be used
Logic
Logic
C8051F410/1/2/3
(asynchronous output)
(asynchronous output)
(synchronous output)
(synchronous output)
CP0A
CP1A
CP0
CP1
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