C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 232
C8051F411-GMR
Manufacturer Part Number
C8051F411-GMR
Description
Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F410DK.pdf
(270 pages)
Specifications of C8051F411-GMR
Processor Series
C8051F4x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
20
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F410DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 20 Channel
On-chip Dac
12 bit, 2 Channel
Package
28QFN EP
Device Core
8051
Family Name
C8051F41x
Maximum Speed
50 MHz
Ram Size
2.25 KB
Operating Supply Voltage
1.8|2.5|3.3|5 V
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
C8051F411-GMR
Manufacturer:
SiliconL
Quantity:
3 000
Part Number:
C8051F411-GMR
Manufacturer:
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Quantity:
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C8051F410/1/2/3
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to
“18.1. Priority Crossbar Decoder” on page 149
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 24.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 12.7. “IT01CF: INT0/INT1
Configuration” on page 118). Setting GATE0 to ‘1’ allows the timer to be controlled by the external input
signal /INT0 (see
measurements.
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 12.7. “IT01CF: INT0/INT1 Configuration” on page 118).
232
Section “12.4. Interrupt Register Descriptions” on page 112
Figure 24.1. T0 Mode 0 Block Diagram
TR0
0
1
1
1
GATE0
X
0
1
1
X = Don't Care
Rev. 1.1
for information on selecting and configuring external I/O
/INT0
X
X
0
1
Counter/Timer
Disabled
Disabled
Enabled
Enabled
IT01CF
), facilitating pulse width
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