C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 123

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

14.2. 32-bit CRC Algorithm
The C8051F41x CRC unit calculates the 32-bit CRC using a poly of 0x04C11DB7. The CRC-32 algorithm
is "reflected", meaning that all of the input bytes and the final 32-bit output are bit-reversed in the process-
ing engine. The following is a description of a simplified CRC algorithm that produces results identical to
the hardware:
For example, the 32-bit 'F41x CRC algorithm can be described by the following code:
unsigned long UpdateCRC (unsigned long CRC_acc, unsigned char CRC_input)
{
}
The following table lists several input values and the associated outputs using the 32-bit 'F41x CRC algo-
rithm (an initial value of 0xFFFFFFFF is used):
unsigned char i; // loop counter
#define POLY 0xEDB88320 // bit-reversed version of the poly 0x04C11DB7
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ CRC_input;
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
//
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
}
// Return the final remainder (CRC value)
return CRC_acc;
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x00000001) == 0x00000001)
{
}
else
{
}
Step 1. XOR the least-significant byte of the current CRC result with the input byte. If this is the
Step 2. Right-shift the CRC result.
Step 3. If the LSB of the CRC result is set, XOR the CRC result with the reflected polynomial
Step 4. Repeat at Step 2 for the number of input bits (8). 
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc >> 1;
CRC_acc ^= POLY;
// if not, just shift the CRC value
CRC_acc = CRC_acc >> 1;
first iteration of the CRC unit, the current CRC result will be the set initial value
(0x00000000 or 0xFFFFFFFF).
(0xEDB88320).
Rev. 1.1
C8051F410/1/2/3
123