C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 133

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a read),
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
RTC0RE FERROR C0RSEF
R/W
Bit7
read-modify-write instructions read and modify the source enable only. [This applies to bits:
RTC0RE, C0RSEF, SWRSF, MCDRSF, PORSF].
RTC0RE: smaRTClock (Real Time Clock) Reset Enable and Flag.
0: Read: Source of last reset was not a smaRTClock alarm or oscillator fail event.
1: Read: Source of last reset was a smaRTClock alarm or oscillator fail event.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0.
1: Read: Source of last reset was Comparator0.
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit.
1: Read: Source of last was a write to the SWRSF bit.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout.
1: Read: Source of last reset was a Missing Clock Detector timeout.
detected.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the V
monitor as a reset source. Note: writing ‘1’ to this bit before the V
and stabilized may cause a system reset. See register VDM0CN (SFR Definition 15.1)
0: Read: Last reset was not a power-on or V
1: Read: Last reset was a power-on or V
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
Write: smaRTClock is not a reset source.
Write: smaRTClock is a reset source.
Write: Comparator0 is not a reset source.
Write: Comparator0 is a reset source (active-low).
Write: No Effect.
Write: Forces a system reset.
Write: Missing Clock Detector disabled.
Write: Missing Clock Detector enabled; triggers a reset if a missing clock condition is
Write: V
Write: V
Bit6
R
DD
DD
SFR Definition 15.2. RSTSRC: Reset Source
monitor is not a reset source.
monitor is a reset source.
R/W
Bit5
SWRSF
R/W
Bit4
WDTRSF MCDRSF
Rev. 1.1
Bit3
DD
R
monitor reset; all other reset flags indeterminate.
DD
monitor reset.
R/W
Bit2
C8051F410/1/2/3
PORSF
R/W
Bit1
DD
SFR Address:
PINRSF
monitor is enabled
Bit0
R
0xEF
Reset Value
Variable
DD
133