C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 249

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

25. Programmable Counter Array (PCA0)
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled (See
Crossbar Decoder” on page 149
a programmable timebase that can select between seven sources: system clock, system clock divided by
four, system clock divided by twelve, the external oscillator clock source divided by 8, smaRTClock Clock
divided by 8, Timer 0 overflow, or an external clock signal on the ECI input pin. Each capture/compare
module may be configured to operate independently in one of six modes: Edge-Triggered Capture, Soft-
ware Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each mode is described in
Section “25.2. Capture/Compare Modules” on page 251
through the system controller's Special Function Registers. The PCA block diagram is shown in
Figure 25.1
Important Note: The PCA Module 5 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled .
See
Section 25.3
Capture/Compare
Module 0
SYSCLK/12
Timer 0 Overflow
SYSCLK
External Clock/8
smaRTClock/8
SYSCLK/4
ECI
for details.
Capture/Compare
Module 1
CLOCK
MUX
PCA
Figure 25.1. PCA Block Diagram
for details on configuring the Crossbar). The counter/timer is driven by
16-Bit Counter/Timer
Capture/Compare
Module 2
Crossbar
Port I/O
Rev. 1.1
Capture/Compare
). The PCA is configured and controlled
Module 3
C8051F410/1/2/3
Capture/Compare
Module 4
Section “18.1. Priority
Capture/Compare
Module 5
249