C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 168
C8051F411-GMR
Manufacturer Part Number
C8051F411-GMR
Description
Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F410DK.pdf
(270 pages)
Specifications of C8051F411-GMR
Processor Series
C8051F4x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
20
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F410DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 20 Channel
On-chip Dac
12 bit, 2 Channel
Package
28QFN EP
Device Core
8051
Family Name
C8051F41x
Maximum Speed
50 MHz
Ram Size
2.25 KB
Operating Supply Voltage
1.8|2.5|3.3|5 V
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
Details
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19.2. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys-
tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 19.1. A
10 M resistor also must be wired across the XTAL1 and XTAL2 pins for the crystal/resonator configura-
tion. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as
shown in Option 2, 3, or 4 of Figure 19.1. The type of external oscillator must be selected in the OSCXCN
register, and the frequency control bits (XFCN) must be selected appropriately (see SFR
Definition 19.3. OSCXCN: External Oscillator Control).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P1.0 and P1.1 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P1.1 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pins used by the oscillator circuit; see
Section “18.1. Priority Cross-
bar Decoder” on page 149
for Crossbar configuration. Additionally, when using the external oscillator cir-
cuit in crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog
inputs (with ‘1's in the corresponding Port Latch). In CMOS clock mode, the associated pin should be con-
figured as a digital input . See
Section “18.2. Port I/O Initialization” on page 151
for details on Port
input mode selection.
The frequency of the external oscillator can be measured with respect to the smaRTClock Oscillator using
Timer 2 or Timer 3. Section “
24.2.3. External/smaRTClock Capture Mode
” on page
241
shows how this
can be accomplished.
19.2.1. Clocking Timers Directly Through the External Oscillator
The external oscillator source divided by eight is a clock option for the timers (
Section “24. Timers” on
page 231
) and the Programmable Counter Array (PCA) (
Section “25. Programmable Counter Array
(PCA0)” on page 249
). When the external oscillator is used to clock these peripherals, but is not used as
the system clock, the external oscillator frequency must be less than or equal to the system clock fre-
quency. In this configuration, the clock supplied to the peripheral (external oscillator / 8) is synchronized
with the system clock; the jitter associated with this synchronization is limited to ±0.5 system clock cycles.
19.2.2. External Crystal Example
If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be
configured as shown in Figure 19.1, Option 1. The External Oscillator Frequency Control value (XFCN)
should be chosen from the Crystal column of the table in SFR Definition 19.3. For example, a 12 MHz crys-
tal requires an XFCN setting of 111b.
168
Rev. 1.1
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