C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 6

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

C8051F410/1/2/3
22. UART0.................................................................................................................... 207
23. Enhanced Serial Peripheral Interface (SPI0)...................................................... 217
24. Timers.................................................................................................................... 231
25. Programmable Counter Array (PCA0) ................................................................ 249
6
21.4.Using the SMBus............................................................................................ 194
21.5.SMBus Transfer Modes.................................................................................. 201
21.6.SMBus Status Decoding................................................................................. 204
22.1.Enhanced Baud Rate Generation................................................................... 208
22.2.Operational Modes ......................................................................................... 209
22.3.Multiprocessor Communications .................................................................... 210
23.1.Signal Descriptions......................................................................................... 218
23.2.SPI0 Master Mode Operation ......................................................................... 219
23.3.SPI0 Slave Mode Operation ........................................................................... 220
23.4.SPI0 Interrupt Sources ................................................................................... 221
23.5.Serial Clock Timing......................................................................................... 221
23.6.SPI Special Function Registers ...................................................................... 222
24.1.Timer 0 and Timer 1 ....................................................................................... 231
24.2.Timer 2 ........................................................................................................... 239
24.3.Timer 3 ........................................................................................................... 244
25.1.PCA Counter/Timer ........................................................................................ 250
21.3.3.SCL Low Timeout................................................................................... 194
21.3.4.SCL High (SMBus Free) Timeout .......................................................... 194
21.4.1.SMBus Configuration Register............................................................... 195
21.4.2.SMB0CN Control Register ..................................................................... 198
21.4.3.Data Register ......................................................................................... 201
21.5.1.Master Transmitter Mode ....................................................................... 201
21.5.2.Master Receiver Mode ........................................................................... 202
21.5.3.Slave Receiver Mode ............................................................................. 203
21.5.4.Slave Transmitter Mode ......................................................................... 204
22.2.1.8-Bit UART ............................................................................................. 209
22.2.2.9-Bit UART ............................................................................................. 210
23.1.1.Master Out, Slave In (MOSI).................................................................. 218
23.1.2.Master In, Slave Out (MISO).................................................................. 218
23.1.3.Serial Clock (SCK) ................................................................................. 218
23.1.4.Slave Select (NSS) ................................................................................ 218
24.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 231
24.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 233
24.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 233
24.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 234
24.2.1.16-bit Timer with Auto-Reload................................................................ 239
24.2.2.8-bit Timers with Auto-Reload................................................................ 240
24.2.3.External/smaRTClock Capture Mode..................................................... 241
24.3.1.16-bit Timer with Auto-Reload................................................................ 244
24.3.2.8-bit Timers with Auto-Reload................................................................ 245
24.3.3.External/smaRTClock Capture Mode..................................................... 246
Rev. 1.1