C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 145

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

17. External RAM
The C8051F41x devices include 2048 bytes of RAM mapped into the external data memory space. All of
these address locations may be accessed using the external move instruction (MOVX) and the data
pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit
address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Mem-
ory Interface Control Register (EMI0CN as shown in SFR Definition 17.1). Note: the MOVX instruction is
also used for writes to the Flash memory. See
MOVX instruction accesses XRAM by default.
For a 16-bit MOVX operation (@DPTR), the upper 5-bits of the 16-bit external data memory address word
are "don't cares.” As a result, the RAM is mapped modulo style over the entire 64 k external data memory
address range. For example, the XRAM byte at address 0x0000 is shadowed at addresses 0x0800,
0x1000, 0x1800, 0x2000, etc. This is a useful feature when performing a linear memory fill, as the address
pointer doesn't have to be reset when reaching the RAM block boundary.
Bits 7–3: UNUSED. Read = 00000b. Write = don’t care.
Bits 2–0: PGSEL: XRAM Page Select.
R/W
Bit7
-
SFR Definition 17.1. EMI0CN: External Memory Interface Control
The EMI0CN register provides the high byte of the 16-bit external data memory address
when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. Since
the upper (unused) bits of the register are always zero, the PGSEL determines which page
of XRAM is accessed.
For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed.
R/W
Bit6
-
R/W
Bit5
-
R/W
Bit4
-
Section “16. Flash Memory” on page 135
Rev. 1.1
R/W
Bit3
-
R/W
Bit2
C8051F410/1/2/3
PGSEL
R/W
Bit1
SFR Address:
R/W
Bit0
for details. The
0xAA
00000000
Reset Value
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