AD9995KCP Analog Devices Inc, AD9995KCP Datasheet - Page 18

• Manufacturer Part Number: AD9995KCP
• Description: IC CCD SIGNAL PROCESSOR 56-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9995KCP

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 30mA
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

Vertical Sequences (VSEQ)
The vertical sequences are created by selecting one of the 10
V-pattern groups and adding repeats, start position, and hori-
zontal clamping and blanking information. Up to 10 V-sequences
can be programmed, each using the registers shown in Table VI.
Figure 17 shows how the different registers are used to generate
each V-sequence.
The VPATSEL register selects which V-pattern group will be
used in a given V-sequence. The basic V-pattern group can have
repetitions added, for high speed line shifts or line binning, by
using the VPATREPO and VPATREPE registers. Generally, the
same number of repetitions are programmed into both registers,
but if a different number of repetitions is required on odd and
Register
VPATSEL
VMASK
VPATREPO
VPATREPE
VPATSTART
HDLEN
AD9995
CLPOB
V1–V6
HBLK
PBLK
Length
4b
2b
12b
12b
12b
12b
HD
Table VI. V-Sequence Registers (see Tables III and IV for HBLK, CLPOB, PBLK Registers)
PROGRAMMABLE SETTINGS FOR EACH V-SEQUENCE:
1. START POSITION IN THE LINE OF SELECTED V-PATTERN GROUP
2. HD LINE LENGTH
3. V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP
4. NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED)
5. START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS
6. MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL
Range
0–9 V-Pattern Group #
0–3 Mask Mode
0–4095 # of Repeats
0–4095 # of Repeats
0–4095 Pixel Location
0–4095 # of Pixels
6
V-PATTERN GROUP
1
Figure 17. V-Sequence Programmability
3
5
VPAT REP 2
Description
Selected V-Pattern Group for Each V-Sequence.
Enables the Masking of V1–V6 Outputs at the Locations Specified by
the FREEZE/RESUME Registers. 0 = No Mask, 1 = Enable
FREEZE1/RESUME1, 2 = Enable FREEZE2/RESUME2, 3 = Enable
both 1 and 2.
Number of Repetitions for the V-Pattern Group for Odd Lines.
If no odd/even alternation is required, set to VPATREPE.
Number of Repetitions for the V-Pattern Group for Even Lines.
If no odd/even alternation is required, set to VPATREPO.
Start Position for the Selected V-Pattern Group.
HD Line Length for Lines in Each V-Sequence.
4
–18–
2
even lines, separate values may be used for each register (see
the V-Sequence Line Alternation section). The VPATSTART
register specifies where in the line the V-pattern group will start.
The VMASK register is used in conjunction with the FREEZE/
RESUME registers to enable optional masking of the V-outputs.
Either or both of the FREEZE1/RESUME1 and FREEZE2/
RESUME2 registers can be enabled.
The line length (in pixels) is programmable using the HDLEN
registers. Each V-sequence can have a different line length to
accommodate various image readout techniques. The maximum
number of pixels per line is 4096. Note that the last line of the
field is separately programmable using the HDLAST register
located in the Field register section.
VPAT REP 3
4
REV. 0