AD9995KCP Analog Devices Inc, AD9995KCP Datasheet - Page 39

• Manufacturer Part Number: AD9995KCP
• Description: IC CCD SIGNAL PROCESSOR 56-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9995KCP

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 30mA
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

Updating New Register Values
The AD9995’s internal registers are updated at different times,
depending on the particular register. Table XV summarizes the
four different types of register updates:
1. SCK Updated: Some of the registers in Bank 1 are updated
2. VD Updated: Most of the registers in Bank 1, as well as the
Update Type
SCK Updated
VD Updated
SG Line Updated
SCP Updated
REV. 0
The Bank Select register (Addr. 0x7F in Bank 1 and 2) is also
immediately, as soon as the 24th data bit (D23) is written.
These registers are used for functions that do not require gat-
ing with the next VD boundary, such as power-up and reset
functions. These registers are lightly shaded in gray in the
Bank 1 register list.
SCK updated.
Field registers in Bank 2, are updated at the next VD falling
edge. By updating these values at the next VD edge, the cur-
rent field will not be corrupted and the new register values
will be applied to the next field. The Bank 1 register updates
may be further delayed past the VD falling edge by using
the UPDATE register (Addr. 0x19). This will delay the VD
updated register updates to any HD line in the field. Note that
the Bank 2 registers are not affected by the UPDATE register.
SERIAL
WRITE
V1–V6
VSG
VD
HD
Register Bank
Bank 1 Only
Bank 1 and Bank 2
Bank 1 Only
Bank 2 Only
Figure 42. Register Update Locations (SeeTable XV for Definitions)
UPDATED
SCK
SCP 0
USE VSEQ2
UPDATED
REGION 0
VD
Table XV. Register Update Locations
Description
Register is immediately updated when the 24th data bit (D23) is clocked in.
Register is updated at the VD falling edge. VD updated registers in Bank 1 may be
delayed further by using the UPDATE register at Address 0x19 in Bank 1. Bank 2
updates will not be affected by the UPDATE register.
Register is updated at the HD falling edge at the end of the SG-active line.
Register is updated at the next SCP when the register will be used.
SCP 1
UPDATED
SGLINE
SGLINE
USE VSEQ3
REGION 1
SG
–39–
SCP 2
USE VSEQ5
UPDATED
3. SG-Line Updated: A few of the registers in Bank 1 are
4. SCP Updated: In Bank 2, all of the V-pattern group and
SCP
updated at the end of the SG active line, at the HD falling
edge. These are the registers to control the SUBCK signal so
that the SUBCK output will not be updated until after the SG
line has been completed. These registers are darkly shaded in
gray in the Bank 1 register list.
V-sequence registers (Addr. 0x00 through 0xCF, exclud-
ing 0x7F) are updated at the next SCP, where they will
be used. For example, in Figure 42, this field has selected
Region 1 to use V-Sequence 3 for the vertical outputs. This
means that a write to any of the V-Sequence 3 registers, or
any of the V-pattern group registers that are referenced by
V-Sequence 3 will be updated at SCP1. If multiple writes
are done to the same register, the last one done before SCP1
will be the one that is updated. Likewise, register writes to
any V-Sequence 5 registers will be updated at SCP2, and
register writes to any V-Sequence 8 registers will be updated
at SCP3.
REGION 2
SCP 3
USE VSEQ8
REGION 3
SCP 0
AD9995