AD9995KCP Analog Devices Inc, AD9995KCP Datasheet - Page 31

• Manufacturer Part Number: AD9995KCP
• Description: IC CCD SIGNAL PROCESSOR 56-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9995KCP

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 30mA
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9995 signal processing chain is shown in Figure 33.
Each processing step is essential in achieving a high quality image
from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V, to be compatible with the 3 V supply
voltage of the AD9995.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 7 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and level of the CCD signal, respectively. The placement of
the SHP and SHD sampling edges is determined by the setting
of the SAMPCONTROL register located at Addr. 0x63. Place-
ment of these two clock signals is critical in achieving the best
performance from the CCD.
Variable Gain Amplifier
The VGA stage provides a gain range of 6 dB to 42 dB, program-
mable with 10-bit resolution through the serial digital interface.
The minimum gain of 6 dB is needed to match a 1 V input signal
REV. 0
0.1F
CCDIN
DC RESTORE
1.5V
SHP
CDS
SHP SHD
GENERATION
PRECISION
SHD
Figure 33. Analog Front End Functional Block Diagram
TIMING
PHASE
DOUT
REGISTER
VGA GAIN
CLPOB PBLK
6dB–42dB
GENERATION
VGA
TIMING
V-H
–31–
with the ADC full-scale range of 2 V. When compared to 1 V
full-scale systems, the equivalent gain range is 0 dB to 36 dB.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain can be calculated for any gain register value by
using the equation
where the code range is 0 to 1023.
DAC
42
36
30
24
18
12
DIGITAL
6
FILTER
0
OPTICAL BLACK
INTERNAL
CLAMP
Gain dB
1.0V
12-BIT
REFB
127
1.0F
ADC
V
REF
Figure 34. VGA Gain Curve
2V FULL SCALE
( ) (
1.0F
2.0V
REFT
255
CLAMP LEVEL
VGA GAIN REGISTER CODE
REGISTER
=
383
0 0351
.
8
CLPOB
511
AD9995
OUTPUT
LATCH
DATA
×
PBLK
Code
639
PHASE
DOUT
)
+
767
6
12
dB
AD9995
895
DOUT
1023