AD9995KCP Analog Devices Inc, AD9995KCP Datasheet - Page 36

• Manufacturer Part Number: AD9995KCP
• Description: IC CCD SIGNAL PROCESSOR 56-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9995KCP

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 30mA
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

CIRCUIT LAYOUT INFORMATION
The AD9995 typical circuit connection is shown in Figure 38.
The PCB layout is critical in achieving good image quality from
the AD999x products. All of the supply pins, particularly the
AVDD1, TCVDD, RGVDD, and HVDD supplies, must be
decoupled to ground with good quality, high frequency chip
capacitors. The decoupling capacitors should be located as
close as possible to the supply pins and should have a very low
impedance path to a continuous ground plane. There should
also be a 4.7 µF or larger value bypass capacitor for each main
supply—AVDD, RGVDD, HVDD, and DRVDD—although
this is not necessary for each individual pin. In most applications,
it is easier to share the supply for RGVDD and HVDD, which
may be done as long as the individual supply pins are separately
bypassed. A separate 3 V supply may also be used for DRVDD,
but this supply pin should still be decoupled to the same ground
plane as the rest of the chip. A separate ground for DRVSS is
not recommended. It is recommended that the exposed paddle
on the bottom of the package be soldered to a large pad, with
multiple vias connecting the pad to the ground plane.
The analog bypass pins (REFT, REFB) should also be carefully
decoupled to ground as close as possible to their respective pins.
The analog input (CCDIN) capacitor should also be located
close to the pin.
AD9995
DATA OUTPUTS
VSUB TO CCD
SUPPLY
DRIVER
3V
4.7F
12
+
EXTERNAL SYNC FROM ASIC/DSP
0.1F
LINE/FIELD/DCLK TO ASIC/DSP
DRVDD
DRVSS
SUBCK 11
VSUB 10
D10
D11
D5
D6
D7
D8
D9
V1 12
V2 13
V3 14
1
2
3
4
5
6
7
8
9
ANALOG
SUPPLY
Figure 38.Typical Circuit Configuration
PIN 1
IDENTIFIER
3V
3
TOP VIEW
AD9995
TO V-DRIVER
VSG1–VSG4,
12
SUBCK
V1–V4,
–36–
0.1F
The H1–H4 and RG traces should be designed to have low
inductance to avoid excessive distortion of the signals. Heavier
traces are recommended because of the large transient cur-
rent demand on H1–H4 by the CCD. If possible, locating the
AD9995 physically closer to the CCD will reduce the inductance
on these lines. As always, the routing path should be as direct as
possible from the AD9995 to the CCD.
The AD9995 also contains an on-chip oscillator for driving an
external crystal. Figure 39 shows an example application using
a typical 24 MHz crystal. For the exact values of the external
resistors and capacitors, it is best to consult with the crystal
manufacturer’s data sheet.
0.1F
42
41
40
39
38
37
36
35
32
31
30
29
34
33
Figure 39. Crystal Driver Application
AD9995
SDI
SL
REFB
REFT
AVSS
CCDIN
AVDD
CLI
TCVSS
RGVDD
RG
RGVSS
CLO
TCVDD
20pF
TO STROBE CIRCUIT
TO MECHANICAL SHUTTER CIRCUIT
35
1F
1F
CLI
3
0.1F
0.1F
SERIAL INTERFACE TO ASIC OR DSP
0.1F
24MHz
1M
XTAL
0.1F
5
+
+
4.7F
4.7F
D 1 0
34
+
4.7F
RG, H1–H4 TO CCD
3V
H1–H4
SUPPLY
500M
CLO
20pF
MASTER CLOCK INPUT
OUTPUT FROM CCD
3V
ANALOG
SUPPLY
3V
RG
SUPPLY
REV. 0