PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 102

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3
Figure 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS
3.3V AC SPECIFICATIONS
1. See Figure 17-1 PCI Signal Timing Measurement Conditions.
2. All primary interface signals are synchronized to P_CLK. All secondary interface
3. Point-to-point signals are P_REQ#, S1_REQ#[7:0], S2_REQ#[6:0], P_GNT#,
4. REQ# signals have a setup of 10 and GNT# signals have a setup of 12.
Symbol
Tsu
Tsu(ptp)
Th
Tval
Tval(ptp)
Ton
Toff
signals are synchronized to either S1_CLKOUT or S2_CLKOUT.
S1_GNT#[7:0], S2_GNT#[6:0], HSLED, HS_SW#, HS_EN, and ENUM#. Bused
signals are P_AD, P_BDE#, P_PAR, P_PERR#, P_SERR#, P_FRAME#, P_IRDY#,
P_TRDY#, P_LOCK#, P_DEVSEL#, P_STOP#, P_IDSEL, S1_AD, S1_CBE#,
S1_PAR, S1_PERR#, S1_SERR#, S1_FRAME#, S1_IRDY#, S1_TRDY#,
S1_LOCK#, S1_devsel#, S1_STOP#, S2_AD, S2_CBE#, S2_PAR, S2_PERR#,
S2_SERR#, S2_FRAME#, S2_IRDY#, S2_TRDY#, S2_LOCK#, S2_DEVSEL#,
and S2_STOP#.
Parameter
Input setup time to CLK – bused signals
Input setup time to CLK – point-to-point
Input signal hold time from CLK
CLK to signal valid delay – bused signals
CLK to signal valid delay – point-to-point
Float to active delay
Active to float delay
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1,2
1,2
1,2
1,2,3
1,2,3
1,2,3
1,2,3
3-PORT PCI-TO-PCI BRIDGE
Min.
3
5
0
2
2
2
-
ADVANCE INFORMATION
66 MHz
Max.
-
-
-
6
6
-
14
09/25/03 Revision 1.09
Min.
7
10, 12
0
2
2
2
-
33 MHz
4
PI7C7300A
Max.
-
-
-
11
12
-
28
Units
ns