PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 73
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PI7C7300ANAE
Manufacturer Part Number
PI7C7300ANAE
Description
IC PCI-PCI BRIDGE 3PORT 272-BGA
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C7300ANAE.pdf
(109 pages)
Specifications of PI7C7300ANAE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
272-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
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14.1.2
14.1.3
DEVICE ID REGISTER – OFFSET 00h
Configuration Register 1
Configuration Register 2
COMMAND REGISTER – OFFSET 04h
Bit
31:16
Bit
31:16
Bit
0
1
2
3
4
5
Device ID
Device ID
Function
Function
Function
I/O Space Enable
Memory Space
Enable
Bus Master
Enable
Special Cycle
Enable
Memory Write
And Invalidate
Enable
VGA Palette
Snoop Enable
Type
R/O
Type
R/O
Type
R/W
R/W
R/W
R/O
R/O
R/W
Page 73 OF 109
Description
Identifies this device as the PI7C7300A. Hardwired as 71E2h.
Description
Identifies this device as the PI7C7300A. Hardwired as 71E3h.
Description
Controls response to I/O access on the primary interface
0: ignore I/O transactions on the primary interface
1: enable response to I/O transactions on the primary interface
Reset to 0
Controls response to memory accesses on the primary interface
0: ignore memory transactions on the primary interface
1: enable response to memory transactions on the primary interface
Reset to 0
Controls ability to operate as a bus master on the primary interface
0: do not initiate memory or I/O transactions on the primary
interface and disable response to memory and I/O transactions on
secondary 1 interface
1: enables PI7C7300A to operate as a master on the primary
interfaces for memory and I/O transactions forwarded from the
secondary interface
Reset to 0
No special cycles defined.
Bit is defined as read only and returns 0 when read
Memory write and invalidate not supported.
Bit is implemented as read only and returns 0 when read (unless
forwarding a transaction for another master)
Controls response to VGA compatible palette accesses
0: ignore VGA palette accesses on the primary
1: enable positive decoding response to VGA palette writes on the
primary interface with I/O address bits AD[9:0] equal to 3C6h,
3C8h, and 3C9h (inclusive of ISA alias; AD[15:10] are not decoded
and may be any value)
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A
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