PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 56

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3
Table 7-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT
During upstream write transactions, when a data parity error is reported on the target
(primary) bus by the target’s assertion of P_PERR#, the following events occur:
!
!
Assertion of P_SERR# is used to signal the parity error condition when the initiator does
not know that the error occurred. Because the data has already been delivered with no
errors, there is no other way to signal this information back to the initiator. If the parity
error has forwarded from the initiating bus to the target bus, P_SERR# will not be
asserted.
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of PI7C7300A to data parity errors are presented
according to the type of transaction in progress. This section organizes the responses of
PI7C7300A to data parity errors according to the status bits that PI7C7300A sets and the
signals that it asserts.
Table 7-1 shows setting the detected parity error bit in the status register, corresponding
to the primary interface. This bit is set when PI7C7300A detects a parity error on the
primary interface.
Primary Detected
Parity Error Bit
0
0
1
0
1
0
0
0
1
0
0
PI7C7300A sets the data parity detected bit in the status register, if the parity error
response bit is set in the command register of the primary interface.
PI7C7300A asserts P_SERR# and sets the signaled system error bit in the status
register, if all the following conditions are met:
-
-
-
-
The SERR# enable bit is set in the command register.
The parity error response bit is set in the bridge control register of the secondary
interface.
The parity error response bit is set in the command register of the primary
interface.
PI7C7300A has not detected the parity error on the secondary (initiator) bus
which the parity error is not forwarded from the secondary bus to the primary
bus.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
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Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
3-PORT PCI-TO-PCI BRIDGE
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
ADVANCE INFORMATION
09/25/03 Revision 1.09
Primary/
Secondary Parity
Error Response
Bits
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
PI7C7300A