PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 8

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15
16
17
18
APPENDIX A: PI7C7300A EVALUATION BOARD USER’S MANUAL....................................... 105
FREQUENTLY ASKED QUESTIONS ................................................................................................. 107
LIST OF TABLES
T
T
T
T
ABLE
ABLE
ABLE
ABLE
15.1
15.2
15.3
16.1
16.2
16.3
16.4
16.5
16.6
17.1
17.2
17.3
17.4
17.5
17.6
18.1
14.1.44
14.1.45
14.1.46
14.1.47
14.1.48
14.1.49
14.1.50
14.1.51
14.1.52
14.1.53
14.1.54
14.1.55
15.3.1
15.3.2
15.3.3
15.3.4
16.1.1
16.1.2
4-1 PCI TRANSACTIONS .............................................................................................................. 21
4-2 WRITE TRANSACTION FORWARDING .............................................................................. 23
4-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES................................... 26
4-4 READ PREFETCH ADDRESS BOUNDARIES....................................................................... 27
BRIDGE BEHAVIOR.................................................................................................................... 92
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ............................................................... 94
ELECTRICAL AND TIMING SPECIFICATIONS................................................................. 100
272-PIN PBGA PACKAGE FIGURE ........................................................................................ 104
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES ............................................................... 92
TRANSACTION ORDERING .................................................................................................... 93
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)..................................... 93
BOUNDARY SCAN ARCHITECTURE..................................................................................... 95
BOUNDARY-SCAN INSTRUCTION SET ................................................................................ 96
TAP TEST DATA REGISTERS .................................................................................................. 97
BYPASS REGISTER ................................................................................................................... 97
BOUNDARY-SCAN REGISTER................................................................................................ 97
TAP CONTROLLER ................................................................................................................... 97
MAXIMUM RATINGS ............................................................................................................. 101
3.3V DC SPECIFICATIONS ..................................................................................................... 101
3.3V AC SPECIFICATIONS ..................................................................................................... 102
PRIMARY AND SECONDARY BUSES AT 66MH
PRIMARY AND SECONDARY BUSES AT 33MH
POWER CONSUMPTION ........................................................................................................ 103
PART NUMBER ORDERING INFORMATION ...................................................................... 104
MASTER ABORT.................................................................................................................. 93
PARITY AND ERROR REPORTING.................................................................................... 93
REPORTING PARITY ERRORS........................................................................................... 94
SECONDARY IDSEL MAPPING ......................................................................................... 94
TAP PINS.............................................................................................................................. 95
INSTRUCTION REGISTER.................................................................................................. 95
SECONDARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER – OFFSET 8Ch
PRIMARY SUCCESSFUL I/O READ COUNTER REGISTER – OFFSET 90h ............... 89
PRIMARY SUCCESSFUL I/O WRITE COUNTER REGISTER – OFFSET 94h.............. 89
PRIMARY SUCCESSFUL MEMORY READ COUNTER REGISTER – OFFSET 98h .... 90
PRIMARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER – OFFSET 9Ch.. 90
CAPABILITY ID REGISTER – OFFSET B0h .................................................................. 90
NEXT POINTER REGISTER – OFFSET B0h .................................................................. 90
SLOT NUMBER REGISTER – OFFSET B0h................................................................... 91
CHASSIS NUMBER REGISTER – OFFSET B0h............................................................. 91
CAPABILITY ID REGISTER – OFFSET C0h .................................................................. 91
NEXT POINTER REGISTER – OFFSET C0h.................................................................. 91
HOT SWAP CONTROL AND STATUS REGISTER – OFFSET C0h ............................... 91
.......................................................................................................................................... 89
Page 8 OF 109
Z
Z
CLOCK TIMING ................................. 103
CLOCK TIMING ................................. 103
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A