PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 68

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12
12.1
12.2
are derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by
a minimum of 0ns. This is the rule for using secondary clocks:
!
RESET
This chapter describes the primary interface, secondary interface, and chip reset
mechanisms.
PRIMARY INTERFACE RESET
PI7C7300A has a reset input, P_RESET#. When P_RESET# is asserted, the following
events occur:
!
!
!
P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and
S_CLK. PI7C7300A is not accessible during P_RESET#. After P_RESET# is de-
asserted, PI7C7300A remains inaccessible for 2
Local Bus Specification Rev 2.2) before the first configuration transaction can be
accepted.
SECONDARY INTERFACE RESET
PI7C7300A is responsible for driving the secondary bus reset signals, S1_RESET# and
S2_RESET#. PI7C7300A asserts S1_RESET# or S2_RESET# when any of the
following conditions is met:
!
!
!
When S1_RESET# or S2_RESET# is asserted, all secondary PCI interface control
signals, including the secondary grant outputs, are immediately 3-stated. Signals S1_AD,
S1_CBE[3:0]#, S1_PAR (S2_AD, S2_CBE[3:0]#, S2_PAR) are driven low for the
Each secondary clock output is limited to no more than one load.
PI7C7300A immediately 3-states all primary and secondary PCI interface signals.
PI7C7300A performs a chip reset.
Registers that have default values are reset.
Signal P_RESET# is asserted. Signal S1_RESET# or S2_RESET# remains
asserted as long as P_RESET# is asserted and does not de-assert until P_RESET# is
de-asserted.
The secondary reset bit in the bridge control register is set. Signal S1_RESET#
or S2_RESET# remains asserted until a configuration write operation clears the
secondary reset bit.
S1_RESET# or S2_RESET# pin is asserted. When S1_RESET# or S2_RESET# is
asserted, PI7C7300A immediately 3-states all the secondary PCI interface signals
associated with the Secondary S1 or S2 port. The S1_RESET# or S2_RESET# in
asserting and de-asserting edges can be asynchronous to P_CLK.
Page 68 OF 109
25
PCI clocks (T
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
rhfa
09/25/03 Revision 1.09
, page 128 of the PCI
PI7C7300A