PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 35

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.9.1
4.9.2
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the
transaction.
!
STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers
have been made. Indicates that no more data transfers will be made during this
transaction.
!
STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never
be able to complete this transaction. DEVSEL# must be asserted for at least one cycle
during the transaction before the target abort is signaled.
MASTER TERMINATION INITIATED BY PI7C7300A
PI7C7300A, as an initiator, uses normal termination if DEVSEL# is returned by target
within five clock cycles of PI7C7300A’s assertion of FRAME# on the target bus. As an
initiator, PI7C7300A terminates a transaction when the following conditions are met:
!
!
!
!
!
!
If PI7C7300A is delivering posted write data when it terminates the transaction because
the master latency timer expires, it initiates another transaction to deliver the remaining
write data. The address of the transaction is updated to reflect the address of the current
DWORD to be delivered.
If PI7C7300A is pre-fetching read data when it terminates the transaction because the
master latency timer expires, it does not repeat the transaction to obtain more data.
MASTER ABORT RECEIVED BY PI7C7300A
If the initiator initiates a transaction on the target bus and does not detect DEVSEL#
returned by the target within five clock cycles of the assertion of FRAME#, PI7C7300A
terminates the transaction with a master abort. This sets the received-master-abort bit in
the status register corresponding to the target bus.
Target disconnect without data transfer
Target abort
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the
target.
During a prefetchable read transaction, a pre-fetch boundary is reached.
For a posted write transaction, all write data for the transaction is transferred from
data buffers to the target.
For burst transfer, with the exception of “Memory Write and Invalidate”
transactions, the master latency timer expires and the PI7C7300A’s bus grant is de-
asserted.
The target terminates the transaction with a retry, disconnect, or target abort.
Page 35 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A