PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 62

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

signaled to the initiator, the initiator must relinquish the lock on the primary bus, and
therefore the lock is not yet established.
The first locked transaction must be a memory read transaction. Subsequent locked
transactions can be memory read or memory write transactions. Posted memory write
transactions that are a part of the locked transaction sequence are still posted. Memory
read transactions that are a part of the locked transaction sequence are not pre-fetched.
When the locked delayed memory read request is queued, PI7C7300A does not queue
any more transactions until the locked sequence is finished. PI7C7300A signals a target
retry to all transactions initiated subsequent to the locked read transaction that are
intended for targets on the other side of PI7C7300A. PI7C7300A allows any transactions
queued before the locked transaction to complete before initiating the locked transaction.
When the locked delayed memory read request transaction moves to the head of the
delayed transaction queue, PI7C7300A initiates the transaction as a locked read
transaction by de-asserting LOCK# on the target bus during the first address phase, and
by asserting LOCK# one cycle later. If LOCK# is already asserted (used by another
initiator), PI7C7300A waits to request access to the secondary bus until LOCK# is de-
asserted when the target bus is idle. Note that the existing lock on the target bus could
not have crossed PI7C7300A. Otherwise, the pending queued locked transaction would
not have been queued. When PI7C7300A is able to complete a data transfer with the
locked read transaction, the lock is established on the secondary bus.
When the initiator repeats the locked read transaction on the primary bus with the same
address, transaction type, and byte enable bits, PI7C7300A transfers the read data back to
the initiator, and the lock is then also established on the primary bus.
For PI7C7300A to recognize and respond to the initiator, the initiator’s subsequent
attempts of the read transaction must use the locked transaction sequence (de-assert
LOCK# during address phase, and assert LOCK# one cycle later). If the LOCK#
sequence is not used in subsequent attempts, a master timeout condition may result.
When a master timeout condition occurs, SERR# is conditionally asserted (see Section
7.4), the read data and queued read transaction are discarded, and the LOCK# signal is
de-asserted on the target bus.
Once the intended target has been locked, any subsequent locked transactions initiated on
the initiator bus that are forwarded by PI7C7300A are driven as locked transactions on
the target bus.
The first transaction to establish LOCK# must be Memory Read. If the first transaction is
not Memory read, the following transactions behave accordingly:
When PI7C7300A receives a target abort or a master abort in response to the delayed
locked read transaction, this status is passed back to the initiator, and no locks are
established on either the target or the initiator bus. PI7C7300A resumes forwarding
unlocked transactions in both directions.
- Type 0 Configuration Read/Write induces master abort
- Type 1 Configuration Read/Write induces master abort
- I/O Read induces master abort
- I/O Write induces master abort
- Memory Write induces master abort
Page 62 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A