PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 107

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

JP2
JP3
JP1
AD31
GNT
REQ
1
FREQUENTLY ASKED QUESTIONS
! What is the function of SCAN_EN?
! What is the function of SCAN_TM#?
! How do you use the external arbiter?
! What is the purpose of having JP1, JP2, and JP3?
! What is the purpose for having U17, U19, and U20?
! How is the evaluation board constructed?
! What is the function of S_CLKIN?
SCAN_TM# is for full scan test and power on reset for the PLL. SCAN_TM# should be connected to
logic “1” or to an RC path (R1 and C13) during normal operation.
a) Disable the on chip arbiter by connecting S_CFN to logic “1” (JP4 in the 2-3 position).
b) Use S1_REQ#[0] as GRANT and S1_GNT#[0] as REQUEST on the S1 bus.
c) Use S2_REQ#[0] as GRANT and S2_GNT#[0] as REQUEST on the S2 bus.
JP1, JP2, and JP3 are designed for easy access to the primary bus signals. You may connect any of
these pins to an oscilloscope or a logic analyzer for observation. No connection is required for normal
operation. The following table indicates which bus signals correspond to which pins.
U17, U19, and U20 are designed for easy access to the digital ground planes for observation.
The evaluation board is a six-layer PCB. The top and bottom layers (1 and 6) are for signals, power,
and ground routing. Layer 2 and layer 5 are ground planes. Layer 3 is a digital 3.3V power plane.
Layer 4 is a digital 5V power plane with an island of analog 3.3V power.
The S_CLKIN pin is a test pin for the on chip PLL when PLL_TM is set to logic “1”.
to logic “0” or “logic “1” depending on functionality. During normal mode, if SCAN_EN is
connected to logic “0” (JP7 in the 1-2 position), S_CLKIN will be used for PLL test only when
PL_TM is active.
AD29
AD28
AD30
SCAN_EN is for a full scan test or S_CLKIN select. During SCAN mode, SCAN_EN will be driven
2
AD26
AD25
AD27
3
CBE3
AD23
AD24
4
AD21
AD20
AD22
5
AD21
AD20
AD22
6
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FRAME
CBE2
AD24
7
DVSEL
IRDY
IRDY
8
LOCK
PERR
STOP
9
SERR
CBE1
PAR
3-PORT PCI-TO-PCI BRIDGE
10
ADVANCE INFORMATION
AD14
AD13
AD15
11
09/25/03 Revision 1.09
AD11
AD10
AD12
12
PI7C7300A
CBE0
AD8
AD9
13
AD6
AD4
AD7
14
AD5
AD2
AD3
15
GND
AD0
AD1
16