PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 85

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.34
14.1.35
UPSTREAM (S1 or S2 to P) MEMORY LIMIT UPPER 32 BITS
REGISTER – OFFSET 58h
P_SERR# EVENT DISABLE REGISTER – OFFSET 64h
Bit
31:0
Bit
0
1
2
3
4
5
Function
Upstream
Memory Limit
Address
Function
Reserved
Posted Write
Parity Error
Posted Write
Non-Delivery
Target Abort
During Posted
Write
Master Abort On
Posted Write
Delayed Write
Non-Delivery
Type
R/W
Type
R/O
R/W
R/W
R/W
R/W
R/W
Page 85 OF 109
Description
Defines bits [63:32] of the upstream memory limit
Reset to 0
Description
Reserved. Returns 0 when read. Reset to 0
Controls PI7C7300A’s ability to assert P_SERR# when it is unable to
transfer any read data from the target after 2
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set.
1: P_SERR# is not assert if this event occurs.
Reset to 0
Controls PI7C7300A’s ability to assert P_SERR# when it is unable to
transfer delayed write data after 2
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Controls PI7C7300A’s ability to assert P_SERR# when it receives a
target abort when attempting to deliver posted write data.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Controls PI7C7300A’s ability to assert P_SERR# when it receives a
master abort when attempting to deliver posted write data.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Controls PI7C7300A’s ability to assert P_SERR# when it is unable to
transfer delayed write data after 2
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
24
24
attempts.
attempts.
09/25/03 Revision 1.09
24
attempts.
PI7C7300A