PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 15

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3
SECONDARY BUS INTERFACE SIGNALS
Name
P_M66EN
Name
S1_AD[31:0],
S2_AD[31:0]
S1_CBE[3:0],
S2_CBE[3:0]
S1_PAR,
S2_PAR
S1_FRAME#,
S2_FRAME#
Pin #
V18
Pin #
B20, B19, C20,
C19, C18, D20,
D19, D17, E19,
E18, E17, F20,
F19, F17, G20,
G19, L20, L19,
L18, M20, M19,
M17, N20, N19,
N18, N17, P17,
R20, R19, R18,
T20, T19
J4, H1, H2, H3,
H4, G1, G3, G4,
F2, F3, F4, E1, E4,
D1, C1, B1, C5,
B5, D6, C6, B6,
A6, C7, B7, D8,
C8, D9, C9, B9,
A9, D10, C10
E20, G18, K17,
P20
F1, A1, A4, A7
K18,
B4
H20,
D2
Page 15 OF 109
Type
PI
Type
PB
PB
PB
PSTS
Description
Primary Interface 66MHz Operation.
This input is used to specify if PI7C7300A is capable
of running at 66MHz. For 66MHz operation on the
Primary bus, this signal should be pulled “HIGH”. For
33MHz operation on the Primary bus, this signal
should be pulled “LOW”.
S1_M66EN and S2_M66EN will both need to be
“LOW”, forcing both secondary buses to run at 33MHz
also.
Description
Secondary Address/Data. Multiplexed address and
data bus. Address is indicated by S1_FRAME# or
S2_FRAME# assertion. Write data is stable and valid
when S1_IRDY# or S2_IRDY# is asserted and read
data is stable and valid when S1_IRDY# or S2_IRDY#
is asserted. Data is transferred on rising clock edges
when both S1_IRDY# or S2_IRDY# and S1_TRDY#
or S2_TRDY# are asserted. During bus idle,
PI7C7300A drives S1_AD or S2_AD to a valid logic
level when S1_GNT# or S2_GNT# is asserted
respectively.
Secondary Command/Byte Enables. Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. The initiator then drives the byte enables during
data phases. During bus idle, PI7C7300A drives
S1_CBE[3:0] or S2_CBE[3:0] to a valid logic level
when the internal grant is asserted.
Secondary Parity. Parity is even across S1_AD[31:0],
S1_CBE[3:0], and S1_PAR or S2_AD[31:0],
S2_CBE[3:0], and S2_PAR (i.e. an even number of
1’s). S1_PAR or S2_PAR is an input and is valid and
stable one cycle after the address phase (indicated by
assertion of S1_FRAME# or S2_FRAME#) for address
parity. For write data phases, S1_PAR or S2_PAR is
an input and is valid one clock after S1_IRDY#
S2_IRDY# is asserted. For read data phase, S1_PAR
or S2_PAR is an output and is valid one clock after
S1_TRDY# or S2_TRDY# is asserted. Signal S1_PAR
or S2_PAR is tri-stated one cycle after the S1_AD or
S2_AD lines are tri-stated. During bus idle,
PI7C7300A drives S1_PAR or S2_PAR to a valid logic
level when the internal grant is asserted.
Secondary FRAME (Active LOW). Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of
S1_FRAME# or S2_FRAME# indicates the final data
phase requested by the initiator. Before being tri-
stated, it is driven to a de-asserted state for one cycle.
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
In this condition,
PI7C7300A