PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 22

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2
4.3
4.4
4.5
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SINGLE ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and
the bus command is driven on P_CBE[3:0]. PI7C7300A supports the linear increment
address mode only, which is indicated when the lowest two address bits are equal to zero.
If either of the lowest two address bits is nonzero, PI7C7300A automatically disconnects
the transaction after the first data transfer.
DUAL ADDRESS PHASE
A 64-bit address uses two address phases. The first address phase is denoted by
the asserting edge of FRAME#. The second address phase always follows on the
next clock cycle.
For a 32-bit interface, the first address phase contains dual address command code on the
C/BE#[3:0] lines, and the low 32 address bits on the AD[31:0] lines. The second address
phase consists of the specific memory transaction command code on the C/BE#[3:0]
lines, and the high 32 address bits on the AD[31:0] lines. In this way, 64-bit addressing
can be supported on 32-bit PCI buses.
The PCI-to-PCI Bridge Architecture Specification supports the use of dual address
transactions in the prefetchable memory range only. See Section 5.3.2 for a discussion of
prefetchable address space. The PI7C7300A supports dual address transactions in both
the upstream and the downstream direction. The PI7C7300A supports a programmable
64-bit address range in prefetchable memory for downstream forwarding of dual address
transactions. Dual address transactions falling outside the prefetchable address range are
forwarded upstream, but not downstream. Prefetching and posting are performed in a
manner consistent with
the guidelines given in this specification for each type of memory transaction in
prefetchable memory space.
DEVICE SELECT (DEVSEL#) GENERATION
PI7C7300A always performs positive address decoding (medium decode) when
accepting transactions on either the primary or secondary buses. PI7C7300A never does
subtractive decode.
DATA PHASE
The address phase of a PCI transaction is followed by one or more data phases.
A data phase is completed when IRDY# and either TRDY# or STOP# are asserted.
broadcast nature of the special cycle command and the inability to control the
transaction as a target. To generate special cycle transactions on other PCI buses,
either upstream or downstream, Type 1 configuration write must be used.
PI7C7300A neither generates Type 0 configuration transactions on the primary PCI
bus nor responds to Type 0 configuration transactions on the secondary PCI buses.
Page 22 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A