PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 5

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PI7C7300ANAE

Manufacturer Part Number
PI7C7300ANAE
Description
IC PCI-PCI BRIDGE 3PORT 272-BGA
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI7C7300ANAE

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
272-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C7300ANAE
Manufacturer:
Pericom
Quantity:
10 000
TABLE OF CONTENTS
1
2
3
4
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
INTRODUCTION .............................................................................................................................. 11
BLOCK DIAGRAM........................................................................................................................... 12
SIGNAL DEFINITIONS ................................................................................................................... 13
PCI BUS OPERATION ..................................................................................................................... 21
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
4.7.7
4.8.1
4.8.2
4.8.3
4.8.4
4.9.1
4.9.2
4.9.3
4.9.4
4.9.3.1
4.9.3.2
4.9.3.3
4.9.4.1
4.9.4.2
4.9.4.3
SIGNAL TYPES .......................................................................................................................... 13
PRIMARY BUS INTERFACE SIGNALS ................................................................................... 13
SECONDARY BUS INTERFACE SIGNALS............................................................................. 15
CLOCK SIGNALS....................................................................................................................... 17
MISCELLANEOUS SIGNALS ................................................................................................... 17
COMPACT PCI HOT-SWAP SIGNALS..................................................................................... 17
JTAG BOUNDARY SCAN SIGNALS........................................................................................ 18
POWER AND GROUND............................................................................................................. 18
PI7C7300A PBGA PIN LIST ....................................................................................................... 18
TYPES OF TRANSACTIONS..................................................................................................... 21
SINGLE ADDRESS PHASE ....................................................................................................... 22
DUAL ADDRESS PHASE........................................................................................................... 22
DEVICE SELECT (DEVSEL#) GENERATION......................................................................... 22
DATA PHASE ............................................................................................................................. 22
WRITE TRANSACTIONS .......................................................................................................... 23
READ TRANSACTIONS ............................................................................................................ 26
CONFIGURATION TRANSACTIONS ...................................................................................... 30
TRANSACTION TERMINATION ............................................................................................. 34
MEMORY WRITE TRANSACTIONS.................................................................................... 23
MEMORY WRITE AND INVALIDATE TRANSACTIONS.................................................... 24
DELAYED WRITE TRANSACTIONS ................................................................................... 24
WRITE TRANSACTION ADDRESS BOUNDARIES ............................................................ 25
BUFFERING MULTIPLE WRITE TRANSACTIONS........................................................... 26
FAST BACK-TO-BACK WRITE TRANSACTIONS .............................................................. 26
PREFETCHABLE READ TRANSACTIONS......................................................................... 26
NON-PREFETCHABLE READ TRANSACTIONS ............................................................... 27
READ PREFETCH ADDRESS BOUNDARIES.................................................................... 27
DELAYED READ REQUESTS ............................................................................................. 28
DELAYED READ COMPLETION WITH TARGET ............................................................. 28
DELAYED READ COMPLETION ON INITIATOR BUS..................................................... 29
FAST BACK-TO-BACK READ TRANSACTION.................................................................. 30
TYPE 0 ACCESS TO PI7C7300A......................................................................................... 30
TYPE 1 TO TYPE 0 CONVERSION ..................................................................................... 31
TYPE 1 TO TYPE 1 FORWARDING.................................................................................... 32
SPECIAL CYCLES ............................................................................................................... 33
MASTER TERMINATION INITIATED BY PI7C7300A ....................................................... 35
MASTER ABORT RECEIVED BY PI7C7300A .................................................................... 35
TARGET TERMINATION RECEIVED BY PI7C7300A ....................................................... 36
TARGET TERMINATION INITIATED BY PI7C7300A ....................................................... 38
DELAYED WRITE TARGET TERMINATION RESPONSE........................................................ 36
POSTED WRITE TARGET TERMINATION RESPONSE ........................................................... 37
DELAYED READ TARGET TERMINATION RESPONSE ......................................................... 38
TARGET RETRY............................................................................................................................ 38
TARGET DISCONNECT................................................................................................................ 39
TARGET ABORT ........................................................................................................................... 40
Page 5 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A

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