PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 51

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2
7.2.1
7.2.2
!
!
!
DATA PARITY ERRORS
When forwarding transactions, PI7C7300A attempts to pass the data parity condition
from one interface to the other unchanged, whenever possible, to allow the master and
target devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that
occurs when a parity error is detected and the way in which the parity condition is
forwarded across PI7C7300A.
CONFIGURATION WRITE TRANSACTIONS TO
CONFIGURATION SPACE
When PI7C7300A detects a data parity error during a Type 0 configuration write
transaction to PI7C7300A configuration space, the following events occur:
!
!
READ TRANSACTIONS
When PI7C7300A detects a parity error during a read transaction, the target drives data
and data parity, and the initiator checks parity and conditionally asserts PERR#.
For downstream transactions, when PI7C7300A detects a read data parity error on the
secondary bus, the following events occur:
!
!
If the parity error response bit is set in the bridge control register, PI7C7300A does
not claim the transaction with S1_DEVSEL# or S2_DEVSEL#; this may allow the
transaction to terminate in a master abort. If parity error response bit is not set,
PI7C7300A proceeds normally and accepts transaction if it is directed to or across
PI7C7300A.
PI7C7300A sets the detected parity error bit in the secondary status register.
PI7C7300A asserts P_SERR# and sets signaled system error bit in status register, if
both of the following conditions are met:
-
-
If the parity error response bit is set in the command register, PI7C7300A asserts
P_TRDY# and writes the data to the configuration register. PI7C7300A also asserts
P_PERR#. If the parity error response bit is not set, PI7C7300A does not assert
P_PERR#.
PI7C7300A sets the detected parity error bit in the status register, regardless of the
state of the parity error response bit.
PI7C7300A asserts S_PERR# two cycles following the data transfer, if the
secondary interface parity error response bit is set in the bridge control register.
PI7C7300A sets the detected parity error bit in the secondary status register.
The SERR# enable bit is set in the command register.
The parity error response bit is set in the bridge control register.
Page 51 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A