PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 61

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8
8.1
8.2
8.2.1
!
The device-specific P_SERR# status register reports the reason for the assertion of
P_SERR#. Most of these events have additional device-specific disable bits in the
P_SERR# event disable register that make it possible to mask out P_SERR# assertion for
specific events. The master timeout condition has a SERR# enable bit for that event in
the bridge control register and therefore does not have a device-specific disable bit.
EXCLUSIVE ACCESS
This chapter describes the use of the LOCK# signal to implement exclusive access to a
target for transactions that cross PI7C7300A.
CONCURRENT LOCKS
The primary and secondary bus lock mechanisms operate concurrently except when a
locked transaction crosses PI7C7300A. A primary master can lock a primary target
without affecting the status of the lock on the secondary bus, and vice versa. This means
that a primary master can lock a primary target at the same time that a secondary master
locks a secondary target.
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C7300A
For any PCI bus, before acquiring access to the LOCK# signal and starting a series of
locked transactions, the initiator must first check that both of the following conditions are
met:
!
!
The initiator leaves the LOCK# signal de-asserted during the address phase and asserts
LOCK# one clock cycle later. Once a data transfer is completed from the target, the
target lock has been achieved.
LOCKED TRANSACTIONS IN DOWSTREAM DIRECTION
Locked transactions can cross PI7C7300A only in the downstream direction, from the
primary bus to the secondary bus.
When the target resides on another PCI bus, the master must acquire not only the lock on
its own PCI bus but also the lock on every bus between its bus and the target’s bus.
When PI7C7300A detects on the primary bus, an initial locked transaction intended for a
target on the secondary bus, PI7C7300A samples the address, transaction type, byte
enable bits, and parity, as described in Section 4.6.4. It also samples the lock signal. If
there is a lock established between 2 ports or the target bus is already locked by another
master, then the current lock cycle is retried without forward. Because a target retry is
Master timeout on delayed transaction
The PCI bus must be idle.
The LOCK# signal must be de-asserted.
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3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A