PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 78

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.17
14.1.18
14.1.19
MEMORY BASE REGISTER – OFFSET 20h
MEMORY LIMIT REGISTER – OFFSET 20h
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h
Bit
28
29
30
31
Bit
3:0
15:4
Bit
19:16
31:20
Bit
3:0
Function
Received Target
Abort
Received Master
Abort
Received System
Error
Detected Parity
Error
Function
Memory Base
Address [15:4]
Function
Memory Limit
Address [31:20]
Function
64-bit addressing
Type
R/WC
R/WC
R/WC
R/WC
Type
R/O
R/W
Type
R/O
R/W
Type
R/O
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Description
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
Description
Set to 1 (by a master device) whenever transactions on its secondary
(S1 or S2) interface are terminated with target abort
Reset to 0
Set to 1 (by a master) when transactions on its secondary (S1 or S2)
interface are terminated with Master Abort
Reset to 0
Set to 1 when S1_SERR# or S2_SERR# is asserted
Reset to 0
Set to 1 when address or data parity error is detected on the
secondary (S1 or S2) interface
Reset to 0
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be 0.
Reset to 0
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the top address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be FFFFFh.
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A