RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 102

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
3.3
102
Figure 4. Quad 155/51 Mbit/s Line Side Interface Example
The four independent transmit serial clock inputs (TSCI_P0/N0, TSCI_P1/N1, TSCI_P2/N2, and
TSCI_P3/N3) allow the independent configuration of each channel rate. Optionally, a common
clock input (TCCI_P/N) allows using a single timing clock reference to the four channels.
shows a configuration example for quad 155 Mbit/s or 51 Mbit/s. Each transmit channel has been
configured to use an independent input timing reference (TSCI_Pi/Ni, i = 0, 1, 2, 3).
The serial line side interface can also be used when Intel IXF6048 is configured as a single STS-3
(non concatenated) processor. In this configuration, only one serial line side interface (channel 0) is
active.
TTL Single Parallel Line Side Interface
When Intel IXF6048 is configured as a Single 2,488 Mbit/s transceiver (STS-48c/STM-16c/STS-
48/STS-48c), the line side interface I/O can be configured as a TTL single parallel-data interface:
RPDI[31:0] and TPDO[31:0].
The interface data-width can be configured independently for each direction (reception and
transmission). The TTL single parallel receive interface does not require external frame acquisition
circuitry, i.e., the input data bus RPDI[31:0] are not required to carry byte-aligned SONET/SDH
data; Intel IXF6048 performs internal (on-chip) frame acquisition and word rotation. Optionally,
T S D O _ P 0 /N 0
T S C O _ P 0 /N 0
T S D O _ P 1 /N 1
T S C O _ P 1 /N 1
T S D O _ P 2 /N 2
T S C O _ P 2 /N 2
T S D O _ P 3 /N 3
T S C O _ P 3 /N 3
R S D I_ P 0 /N 0
R S C I_ P 0 /N 0
R S D I_ P 2 /N 2
R S C I_ P 2 /N 2
R S D I_ P 1 /N 1
R S C I_ P 1 /N 1
R S D I_ P 3 /N 3
R S C I_ P 3 /N 3
T S C I_ P 0 /N 0
T S C I_ P 1 /N 1
T S C I_ P 2 /N 2
T S C I_ P 3 /N 3
R L O C K 0
R L O C K 2
R L O C K 1
R L O C K 3
Q u a d O C -3 c
(1 5 5 M b it/s )
Q u a d O C -1
(5 1 M b it/s )
IX F 6 0 4 8
o r
A T M /
P O S
Datasheet
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Figure 4