RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 287

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

11.7.10
11.7.11
Datasheet
15:12
15:12
Bit
Bit
10
10
11
11
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
Unused
HptRdi
RcvC2Chg
HptReiOvrFlw
B3OvrFlw
C2Unstable
J1allzero
J1Unstable
J1MsMtch
J1Crc7Err
HptUnEqp
HptSlm
VcAis
Unused
HptRdiEn
RcvC2ChgEn
HptReiOvrFlwEn
B3OvrFlwEn
C2UnstableEn
J1allzeroEn
J1UnstableEn
J1MsMtchEn
IS_HPT—Receive Path (HPT) Interrupt Register ((1cc)D3H)
Each of these bits can cause the chip’s interrupt pin to become active if enabled via the bits in the
Receive Interrupt Enable Register 3.
IE_HPT—Receive Path (HPT) Interrupt Enable ((1cc)D7H)
Name
Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
This bit sets when the register R_HPT_RDI[3:1] bits (filtered received
G1 RDI bits) change (see HptRdiDetCnt = register R_HPT_C1). It
clears when register R_HPT_RDI is read.
This bit sets when there is a change in the R_C2 register. It clears
when that register is read.
This bit sets when the value in the HPTREI_CNT counter rolls over. It
clears when this register, IS_HPT, is read.
This bit sets when the value in the B3_ECNT counter rolls over. It
clears when this register, IS_HPT, is read.
This bit sets when there is a change in the C2UnstableSt bit (register
S_HPT[6]). It clears when this register, IS_HPT, is read.
This bit sets when there is a change in the J1allzeroSt bit (register
S_HPT[6]). It clears when this register, IS_HPT, is read.
This bit sets when there is a change in the J1UnstableSt bit (register
S_HPT[5]). It clears when this register, IS_HPT, is read.
This bit sets when there is a change in the J1MsMtchSt bit (register
S_HPT[4]). It clears when this register, IS_HPT, is read.
This bit sets when there is a change in the J1Crc7St bit (register
S_HPT[3]). It clears when this register, IS_HPT, is read.
This bit sets when there is a change in the HptUneqSt bit (register
S_HPT[2]). It clears when this register, IS_HPT, is read.
This bit sets when there is a change in the HptSlmSt bit (register
S_HPT[1]). It clears when this register, IS_HPT, is read.
This bit sets when there is a change in the VcAisSt bit (register
S_HPT[0]). It clears when this register, IS_HPT, is read.
Active-high enable for the HptRdi interrupt bit.
Active-high enable for the RcvC2Chg interrupt bit.
Active-high enable for the HptReiOvrFlw interrupt bit.
Active-high enable for the B3OvrFlw interrupt bit.
Active-high enable for the C2Unstable interrupt bit.
Active-high enable for the J1allzero interrupt bit.
Active-high enable for the J1Unstable interrupt bit.
Active-high enable for the J1MsMtch interrupt bit.
Description
Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R
R
R
R
R
R
R
R
R
R
R
R
Default
Default
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
287