RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 213

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

10.0
10.1
10.2
Datasheet
Microcontroller Interface
This section contains a description of the asynchronous microprocessor interface. The
microprocessor interface is a generic asynchronous interface, including an address bus (A[10:0]),
data bus (DATA[15:0]), and handshaking pins (WRB/RWB, RDB/E, CSB, and ALE). The
MCUTYPE input pin indicates the type of microprocessor interface to be used—Intel or
Motorola*. There is also an INT output pin that indicates status changes to the microprocessor.
Intel Interface
An Intel interface is selected by driving the MCUTYPE input pin low. It uses the WRB/RWB input
pin as WRB and the RDB/E input pin as RDB.
A read cycle is indicated to the Intel IXF6048 by the microprocessor forcing a low on the RDB pin
with the WRB pin held high.
A write cycle is indicated to the Intel IXF6048 by the microprocessor forcing a low on the WRB
pin with the RDB pin held high.
Both cycles require the CSB pin to be low and the microprocessor to drive the A[10:0] address
pins. In a write cycle, the microprocessor also drives the DATA[15:0] data pins. In a read cycle, the
Intel IXF6048 drives the DATA[15:0] data pins.
When a multiplexed data/address bus is used, the falling edge of the ALE input, latches the address
provided on the muxed bus (the muxed bus is connected to both A[10:0] and DATA[15:0]). If the
address and data are not multiplexed, the ALE pin should be tied high.
Motorola* Interface
A Motorola* interface is selected by driving the MCUTYPE input pin high. It uses the WRB/RWB
input pin as RWB and the RDB/E input pin as E.
A read cycle is indicated to the Intel IXF6048 by the microprocessor forcing a high on the RWB
pin. A write cycle is indicated to the Intel IXF6048 by the microprocessor forcing a low on the
RWR pin.
A low on the E input initiates both cycles. The E input is connected to the E output from the
Motorola* microprocessor and is typically a 50% duty cycle waveform with a frequency derived
from the microprocessor clock.
Both cycles require the CSB pin to be low and the microprocessor to drive the A[10:0] address
pins. In a write cycle, the microprocessor also drives the DATA[15:0] data pins. In a read cycle, the
Intel IXF6048 drives the DATA[15:0] data pins.
When a multiplexed data/address bus is used, the falling edge of the ALE input, latches the address
provided on the muxed bus (the muxed bus is connected to both A[10:0] and DATA[15:0]). If the
address and data are not multiplexed, the ALE pin should be tied high.
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
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