RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 106

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
4.2
106
Line Side
OC-48
Figure 6. OC-48 Repeater Application
Single 2.5 Gbps configuration
OPT
Rx
REPEATER
Application
transmit line) for the "Blue"
Transmit Data Flow
Figure 1
transmitter (lower half of
mapping block, with 32-bit (OC-12/48) or byte (OC-1/3) wide data MDATAi[31:0] and timing
signal for the payload active signal CENi.
The data flow starts with the Transmit Higher order Path termination Processor (THPP block)
which adds the concatenated VC(s) path overhead:
Local Reference (selected
155.52 MHz +/- 20 ppm
(OC-48 CDR)
•
•
•
•
•
2.5 Gbit/s
Receiver
Signal Generation
The 1-, 16-, or 64-byte J1 string is sourced from the microprocessor programmable registers
(Path Trace Buffer) or TPOH serial input. The microprocessor must calculate the CRC-7 byte
of the 16-byte J1 transmit string and store it in the first byte of the registers storing the string.
The B3 byte is calculated internally and inserted. The microprocessor can invert the values of
B3 for system testing purposes.
The C2 byte is sourced from the microprocessor programmable register or TPOH serial input.
The G1 byte is sourced from the microprocessor programmable register, TPOH serial input,
the Transmit Path Alarm serial bus input (TPAL), or from the receive portion of the chip if
automatic RDI and REI insertion is enabled by the microprocessor.
The F2 and F3/Z3 bytes are two optional 64-Kbit/s channels that can be sourced from
dedicated serial accessor from the serial bus TPOH. They may also be internally set to their
default value of either all ‘1’s or all ‘0’s. In the case of a dedicated serial ports, a 64-KHz
reference clock is supplied at TPOWC and an 8-KHz sync pulse at TPOWBYC.
shows the functional blocks of the SONET/SDH Block for the 4 channels. For each
INTERFACE
data+Clock
16 bits
parallel
RLOCK
Alarm
LIU
Figure
Regenerator OverHead Bytes
Configuration and Network
Management Interface
Microprocessor for
Serial Accesses
1), the input interface is the bus coming from the ATM/POS
Programmable
Configuration
Pass Through
IXF6048
Regenerator
2.5 Gbps
SONET
SDH /
JTAG
Port
data+Clock
16 bits
parallel
INTERFACE
LIU
16 -> 1 MUX)
Transmitter
2.5 Gbit/s
(OC-48;
OPT
Tx
Datasheet
Line Side
OC-48