RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 251

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

11.3.4
11.3.5
Datasheet
15:12
15:8
11:0
Bit
Bit
7
6
5
Unused
RcvPWM[11:0]
Unused
XmtSmallMem
XmtFifEmptEOF
XmtDirStatCnf
R_PWM—Receive Programmable Watermark ((0cc)61H)
T_UICNF—Transmit UTOPIA Interface Configuration ((000)50H)
This register configures the transmit UTOPIA interface features that are common to the four
channels.
Name
Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
XmtSmallMem selects the size of the transmit UTOPIA interface
FIFO memory used by channel #0:
'0' = Channel #0’s transmit FIFO size is 16-Kbyte.
'1' = Channel #0’s transmit FIFO size is 2-Kbyte.
XmtSmallMem can be used to force identical behavior in all four
channels.
XmtFifEmptEOF selects when the POS transmitter can start the
transmission of a new packet:
'0' = The POS transmitter starts the transmission of a new packet,
if the FIFO contains an EOF or the FIFO contains a number of
words equal to or greater than the Transmit Initiation Minimum
Level (register T_UIIML).
'1' = The POS transmitter starts the transmission of a new packet,
if the FIFO contains a number of words equal to or greater than the
Transmit Initiation Minimum Level (register T_UIIML).
XmtDirStatCnf configures the TXFA_i (i = 0, 1, 2, 3) outputs in two
different ways:
'1' = Direct status indication mode. The TXFA_i (i = 0, 1, 2, 3)
outputs are always driven.
'0' = Multiplexed status polling. The TXFA_i (i = 0, 1, 2, 3) outputs
are driven only after one (UTOPIA Level 2) or two (UTOPIA Level
3) clock cycles with an address in the TXADDR bus matching the
programmed base-address value UaddrBase[2:0].
The receive programmable watermark RcvPWM is used to control
the assertion and deassertion of the receiver outputs RXPFA and
RXFA_i (i = 0, 1, 2, 3) when the addressed channel works in POS
mode.
RXPFA and RXFA_i (i = 0, 1, 2, 3) are asserted when the FIFO
contains an end-of-packet or contains a number of 32-bit words
equal to or greater than RcvPWM. RXPFA and RXFA_i (i = 0, 1, 2,
3) are deasserted when the FIFO does not contain an end of
packet (see RcvFifEmptEOF in the register R_UICNF) and
contains a number of 32-bit words less than RcvPWM.
Channels 1, 2, and 3: The size of the FIFO is 512 words of 32 bits
(2048 bytes) and only RcvPWM[8:0] are used (9-bit watermark).
RcvPWM[11:9] are unused bits.
Channel 0: The size of the FIFO is 4096 words of 32 bits
(16 Kbytes) and RcvPWM[11:0] are used as a 12-bit watermark.
Description
Description
Type
Type
R/W
R/W
R/W
R/W
Default
Default
00FH
'0'
'0'
'1'
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