RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 340
RCLXT16706FE
Manufacturer Part Number
RCLXT16706FE
Description
Manufacturer
Intel
Datasheet
1.RCLXT16706FE.pdf
(352 pages)
Specifications of RCLXT16706FE
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
340
TXADDR[4:0], TXPADL[2:0],
RXCLK frequency
RXCLK duty cycle
RXADDR[4:0] and RXENB setup time to RXCLK
RXADDR[4:0] and RXENB hold time from RXCLK
RXCLK rising edge to RXDATA[63:0], RXPRTY, RXSOF, RXEOF,
RXPADL[2:0], RXVAL, RXERR, RXPFA, and RXFA_i (i = 0, 1, 2, 3)
propagation delay
RXCLK rising edge to RXDATA[63:32] propagation delay
NOTES:
RXVAL, RXEOF, RXERR,
1. In memory mapped mode (RcvSelMode = 1 in register R_UICNF), t
2. Note that in 64-bit mode t
RXSOF, RXPFA, RXFA_i
RXPADL[2:0], RXPRTY,
TXENB, TXSOF, TXEOF,
RXADDR[4:0], RXENB
TXPFA, TXSFA, TXFA_i
Figure 91. Receive UTOPIA Single Interface Configured for 50 MHz Operation: 64/32/16/8-Bit
Figure 92. Transmit UTOPIA Single Interface Configured for 50 MHz Operation: 64/32/16/8-Bit
Table 48. Receive UTOPIA Single Interface Timings for the Configurations Supporting 50 MHz
TXPRTY, TXERR,
RXDATA[63:0],
TXDATA[63:0],
Data Bus and One/Two Clock Cycle Decode-Response Delay Signals
Data Bus and One/Two Clock Cycle Decode-Response Delay Signals
Operation: 64/32/16/8-Bit Wide Data Bus, One Decode-Response Clock Cycles or
High-Impedance Outputs (Sheet 1 of 2)
RXCLK
TXCLK
ul2Rxpd
Parameter
is different for RXDATA[63:32]
VALID OUTPUT
t
ul2Rxsu
VALID OUTPUT
t
ul2Txsu
VALID INPUT
VALID INPUT
t
ul2Rxpd
t
ul2Txpd
t
ul2Rxh
t
ul2Txh
2
1/f
VALID OUTPUT
1/f
VALID OUTPUT
ul2Rx
ul2Tx
VALID INPUT
ul2Rxsu
VALID INPUT
Symbol
t
t
t
D
t
ul2Rxsu
ul2Rxpd
ul2Rxpd
t
f
ul2Rxh
ul2RxlhZ
ul2Rx
= 5 ns, otherwise t
ul2Rx
t
ul2TxlhZ
4/5
Min
30
1
1
1
1
ul2Rxsu
VALID INPUT
VALID INPUT
Typ
= 4 ns
t
ul2RxhlZ
t
ul2TxhlZ
Max
50
70
14
VALID OUTPUT
6
Datasheet
VALID OUTPUT
Unit
MHz
ns
ns
ns
ns
%
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