RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 187

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

7.1.6
7.1.7
7.1.8
Datasheet
FCS Verification
The Frame Check Sequence (FCS) field is calculated over all bits of the Address, Control,
Protocol, Information, and Padding fields, not including the Flag Sequences nor the FCS field
itself. The FCS field is checked after Control Escape removal (after byte destuffing). The FCS is
received least significant octet first, which contains the coefficient of the highest term. Two
different generating polynomials are defined, the CRC-CCITT (CRC-16)
a
RcvFCSCnf[1:0] (register R_PHCCNF) configures the use of CRC-CCITT, CRC-32, or no-FCS
checking.
When an FCS error is detected, the POS-packet can optionally be marked in the receive FIFO as
errored. RcvFCSErr (register R_PHCCNF) is used to configure whether the packet is marked as
errored or not.
The FCS field can be eliminated (not written into the receive FIFO) or written into the receive
FIFO, depending on the RcvFCSPass bit (register R_PHCCNF). The FCS is always eliminated if
the Address and Control fields are passed to the user (see
Address and Control Fields
RcvACPass (register R_PHCCNF) configures whether the Address and Control fields are
eliminated or passed to the user (written into the receive FIFO) with the PPP frame. RcvACChk
(register R_PHCCNF) enables the checking of the Address and Control fields. The Address field is
compared with FFH and the All-Stations address while the Control field is compared with 03H and
the Unnumbered Information (UI) command, with the Poll/Final (P/F) bit set to '0'. If RcvACChk =
'1', the frames containing Address and Control fields with values different than FFH and 03H are
discarded (not written into the FIFO). A maskable interrupt (RcvACI, register R_POSINT) is
activated when a frame is discarded in this way.
Receive FIFO
The receive FIFO memory (a 2-Kbyte deep FIFO per channel or a 16-Kbyte deep FIFO in a single-
channel application) stores the received POS-packets, providing for the separation of the transport
timing from the system timing. It is then read by the receive POS-UTOPIA interface.
When the receive FIFO overflows (the Link Layer device fails to keep up with the incoming
HDLC frame traffic), the packet being written into the FIFO is marked as errored. This incomplete
POS-packet stored in the FIFO must be discarded by the user. A maskable interrupt (RcvFifoOFI,
register R_POSINT) is activated when the FIFO overflows.
After a receive FIFO overflow condition, the receive HDLC controller stops writing data into the
FIFO until the receive FIFO free available space is equal to or greater than the value specified by
RcvIML[3:0] (register R_PUICNF). RcvIML[3:0] (receive initiation minimum level) is used only
after a receive FIFO overflow and is used to avoid consecutive FIFO overflows (to recover after an
nd the CRC-32:
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
g(X) = 1 + X
g(X) = 1 + X + X
+ X
32
5
+ X
2
12
+ X
+ X
4
+ X
16
5
+ X
7
+ X
8
+ X
Section
10
+ X
11
7.1.7).
+ X
12
+ X
16
+ X
22
+ X
23
+ X
187
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