RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 257

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

11.3.11
11.3.12
Datasheet
15:12
15:8
11:8
Bit
7:4
3:0
Bit
7:4
3:0
Unused
RcvFIFOOFI[3:0]
RcvFifoUFI[3:0]
XmtFifoUFI[3:0]
XmtSOCI[3:0]
XmtPrtyErrI[3:0]
XmtFifoOFI[3:0]
R_UTOINT—Receive UTOPIA Interface Interrupt Register ((000)72H)
T_UTOINT—Transmit UTOPIA Interface Interrupt Register ((000)52H)
Name
Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
RcvFIFOOFI[i] (i = 0, 1, 2, 3) is set to logic one when a receive
FIFO overflow occurs in channel i. This interrupt is meant to be
used when the channel is configured in transparent mode. In ATM
or POS modes, both ATM and POS processors monitor the FIFO
overflow condition.
RcvFifoUFI[i] (i = 0, 1, 2, 3) is set to logic one when a receive FIFO
underflow occurs in channel i, e.g., the Link Layer device attempts
to read a new ATM cell from a FIFO that does not contain a
complete ATM cell (in ATM mode) or attempts to read a word when
the FIFO is empty (in POS mode).
These interrupt bits clear upon reading this register.
XmtFifoUFI[i] (i = 0, 1, 2, 3) are set to logic one when a transmit
FIFO underflow occurs in channel i. These interrupts are meant to
be used in transparent mode. If data is needed from the FIFO to be
mapped into the SPE and the FIFO is empty then the interrupt is
asserted.
XmtSOCI set to logic one when a start of cell (TXSOF input) is
sampled high in an incorrect position, which is any position
different than the first word of an ATM cell.
When TXSOF is sampled high during any position other than the
first word of an ATM cell, XmtSOCI are activated and the FIFO
write address is initialized so the previous incomplete cell is
overwritten by the new cell.
TXSOF is not required to be high when writing the first word of an
ATM cell. If TXSOF is low, when writing the first word of a cell, it is
not considered an error and XmtSOCI are not activated.
These interrupt bits clear upon reading this register.
When the interface is working in quad mode (XmtUMode = '00' in
register T_UICNF), XmtPrtyErrI[i] are set to logic one if a parity
error occurs in channel i.
When working in single mode, the four bits take the same value
and are asserted if a parity error occurs in the data bit.
These interrupt bits clear upon reading this register.
XmtFifoOFI[i] (i = 0, 1, 2, 3) are set to logic one when a transmit
FIFO overflow occurs in channel i, e.g.,the ATM Layer device
attempts to write into a full FIFO.
These interrupt bits are cleared automatically after this register is
read.
Description
Description
Type
Type
R
R
R
R
R
R
Default
Default
0000
0000
0000
0000
0000
0000
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