RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 199

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

8.2.2
Datasheet
Each of the previous configurations requires the use of the RXVAL output. The Link-Layer device
MUST use RXVAL to validate/invalidate the data read from the FIFO. The RXVAL output can be
used in two different modes:
Asserting RXVALCTRL the Link-Layer device indicates that it wants to stop reading the FIFO
after the end of the current packet.
Decode-Response Configuration
RcvDRCnf (global register R_UICNF) configures the decode-response delay for the receive
interface:
When RcvDRCnf = '0', the decode-response delay in the receive UTOPIA interface is one clock
cycle:
When RcvDRCnf = '1', the decode-response delay in the receive UTOPIA interface is two clock
cycles:
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RXENB changes from '1' to '0'. Once the port is selected (RXENB = '0'), the receive address
RXADDR[4:0] can take any value (FIFO status polling using RXPFA).
When configuration bit RcvSelMode = '1' (global register R_UICNF), the receive POS-
UTOPIA interface is controlled as a memory mapped device. There is no selection cycle or
FIFO status polling, just port addressing. The RXPFA output is not used and the status of each
FIFO is indicated using the direct outputs RXFA_0, RXFA_1, RXFA_2, and RXFA_3.
Nothing happens when RXENB = '1'. If RXENB = '0', the interface reads a word from the
FIFO addressed by RXADDR[4:0].
When the bit RcvValCnf (in register R_UICNF) is set to logic zero, RXVAL assertion and
deassertion is based only on the status of the receive FIFO. RXVAL is deasserted when
attempting to read an empty FIFO (receive FIFO underflow). When the Link Layer device
tries to read an empty FIFO, the read command is disregarded and the FIFO is not modified.
The receive FIFO underflow is not considered an error (no data is lost).
When the bit RcvValCnf (in register R_UICNF) is set to logic one, RXVAL is used in the
same way as for RcvValCnf = '0' (invalidation of the output the signals if the FIFO is empty).
In addition, RXVAL is also deasserted after reading the last word of a packet, i.e. the next
word (start of the next packet) is not read from the FIFO. When RXVAL is deasserted, the
conditions FIFO-empty and end-of packet are differentiated using RXEOF. This configuration
allows the Link Layer device to synchronize with the packet boundaries.
The delay from the receive address (RXADDR) to the receive polled frame available signal
(RXPFA) is one clock cycle.
The delay from the receive enable (RXENA) to the receive data (RXDATA[31:0], RXSOF,
RXEOF, RXPADL[1:0], RXERR, RXVAL, and RXPRTY) is one clock cycle.
The delay from the receive address (RXADDR) to the receive polled frame available signal
(RXPFA) is two clock cycles.
The delay from the receive enable (RXENA) to the receive data (RXDATA[31:0], RXSOF,
RXEOF, RXPADL[1:0], RXERR, RXVAL, and RXPRTY) is two clock cycles.
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
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