RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 146

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
146
TSALFR[i] Status
(See
Table 17. TSAL[i] Bus Frame
Figure
High
Low
18)
For each channel, TSAL[i] provides the following information regarding the transmit APS:
TSAL[i], when configured as a ring port, is used to input the line RDI (MS-RDI) and line REI
(MS-REI) information from an external source. In this case, the internal feedback of the remote
defects is disabled. For this purpose, it provides:
Configuration register T_SC_MSOH independently specifies the transmit source of K1, K2 APS,
K2 RDI, and M1 REI as coming from the TSAL input port or not. Note that the TSAL bus may be
used as the transmit source for these bytes only if the TSOHINS input control pin is active-low
during these bytes’ time slots on the TSOH input bus.
The CRC-4 bits located in the 4 last bits of the TSAL frame are computed for data error checking
of the TSAL serial input bus. The CRC-4 calculation is performed over the entire TPAL frame
including the unused bits. The 4-bit CRC-4 calculated word is the remainder after multiplication by
X
replaced by '0's during computation. The remainder result is then compared on a bit-by-bit basis
with the CRC-4 bits received in the last four bits of the same TSAL frame (bit 1 is received first). If
the remainder calculated does not correspond to the CRC-4 bits received, then the checked TSAL
frame (between 2 consecutive frame pulses) is assumed to have some errors. This detected default
sets a maskable interrupt that can be accessed via global register TALBINT.
When TSAL[i] is configured as a codirectional interface, Intel IXF6048 detects the absence of
clock (TSALCK[i]) and/or framing pulse (TSALFR[i]) on the incoming timings. If no input
framing pulse is detected within 250 µs or there is less then 16 clock cycles within 125 µs, then a
maskable interrupt is set that can be accessed via global register TALBINT.
4
and then division (modulo 2) by the generator polynomial X
Time Slot #
— K1 APS input value.
— K2 APS input value.
— The generated REI value to be transmitted.
— The generated RDI defect to be transmitted.
1
2
3
4
5
6
7
8
9
Position
Bit
2:8
1:8
1:8
1:8
1:8
1:8
1:8
1:8
1:4
1
5
6
7
8
Generated RDI to be transmitted
Unused
Generated REI [7:0] to be transmitted
K1[7:0] transmit APS
K2 [7:0] transmit APS
Unused
Unused
Unused
Unused
Unused
CRC-4 bit 1
CRC-4 bit 2
CRC-4 bit 3
CRC-4 bit 4
Content
4
+ X + 1.The CRC-4 bits are
Ring port
APS port
APS port
Control (for data error check)
Control (for data error check)
Control (for data error check)
Control (for data error check)
Ring port
Port Type
Datasheet