RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 97

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

2.1.6
2.1.7
Datasheet
Transmit Byte-Synchronous HDLC Controller (Transmit POS Block)
ATM-UTOPIA Interface
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The number of received frames written into the receive FIFO and not marked as errored
(“good frames”) are counted in a 24-bit counter.
The number of bytes received and written into the receive FIFO are counted in an 32-bit
counter. Intel IXF6048 can be configured to count all the bytes written into the FIFO (good
frames + frames marked as errored) or only the bytes received within good frames.
A 16-bit counter tallies the number of received aborted frames (finishing with an Abort
sequence).
A 16-bit counter tallies the number of received frames with an incorrect FCS field.
A 16-bit counter tallies the number of received frames that have been partially lost due to a
FIFO overrun.
Two 16-bit counters tally the number of frames received and written into the receive FIFO that
have packet lengths which are smaller/longer than the programmed minimum/maximum
packet length.
Maps byte-synchronous HDLC frames into the transmitted STS-48c/STM-16c/STS-48/STM-
16/STS-12c/STM-4c/STS-12/STM-4/STS-3c/STM-1/STS-1 signal.
Read control of four, independent, 2K-byte deep, packet-rate decoupling, FIFO memories
(Single non-concatenated transceiver and Quad transceiver modes).
Read control of one, 16K-byte deep, packet-rate decoupling, FIFO memory (Single
concatenated mode).
HDLC frame generation.
HDLC Address and Control fields can be generated or read from the FIFO (part of the packet).
FCS-16/32 generation.
Control Escape stuffing insertion (byte stuffing).
Two different transmit flow control methods (using interframe FLAG character insertion).
SPE self-synchronous scrambling, after frame mapping.
The number of packets read from the transmit FIFO and transmitted into HDLC frames are
counted in a 24-bit counter (only the non aborted frames).
The number of bytes read from the transmit FIFO and transmitted into the generated HDLC
frames are counted in an 32-bit counter (all the bytes or only the not-aborted frames).
The number of HDLC frames that have been aborted by the user are counted in a 16-bit
counter.
The number of HDLC frames that have been aborted by the HDLC controller, due to a
transmit FIFO underflow, are counted in a 16-bit counter.
Supports all different versions of the ATM-Forum UTOPIA interface:
— UTOPIA Level 3 with 64-bit data bus
— UTOPIA Level 3 with 32-bit data bus
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
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